• 제목/요약/키워드: Voltage deviation

검색결과 315건 처리시간 0.026초

Input Current Characteristics of a Three-Phase Diode Rectifier with Capacitive Filter Under Line Voltage Unbalance Condition

  • Jeong Seung-Gi;Lee Dong-Ki;Park Ki-Won
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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    • pp.808-815
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    • 2001
  • The three-phase diode rectifier with a capacitive filter is highly sensitive to line voltage unbalance, and may cause significantly unbalanced line currents even under slightly unbalanced voltage condition. This paper presents an analysis of this 'unbalance amplification' effect for an ideal rectifier circuit without ac-and dc-side inductors. The voltage unbalance is modeled by introducing a deviation voltage superimposed on balanced three-phase line voltages. With proper approximations, closed-form expressions for symmetrical components of the line current and current unbalance factor are derived in terms of the voltage unbalance factor, filter reactance, and load current. The validity of analytical predictions is confirmed by simulation.

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MAG용접의 Arc안정성에 미치는 Si의 영향 (Effect of Si on Arc Stability of MAG Welding)

  • 안영호;이종봉;엄동석
    • Journal of Welding and Joining
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    • 제16권6호
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    • pp.52-58
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    • 1998
  • The effect of Si content in welding wires on th arc stability was investigate, in the region of short circuit transfer and spray transfer. In the region of short circuit transfer, with increasing Si content, average arcing time and average short circuit time were increased. Therefore, droplet transfer frequency was decreased, due to the increase of arcing time and peak current at the moment of arc-reiginition was increased, due to the increase of short circuit time. In the region of spray transfer, the fluctuations of arc current and arc voltage was the most stable in wire with Si content of about 00.60 wt.%.

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복합배전계통에서 분산형전원의 설치 및 운영을 위한 Fuzzy-GA 응용 (Fuzzy-GA Application for Allocation and Operation of Dispersed Generation Systems in Composite Distribution Systems)

  • 김규호;이유정;이상봉;유석구
    • 대한전기학회논문지:전력기술부문A
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    • 제52권10호
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    • pp.584-592
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    • 2003
  • This paper presents a fuzzy-GA method for the allocation and operation of dispersed generator systems(DGs) based on load model in composite distribution systems. Groups of each individual load model consist of residential, industrial, commercial, official and agricultural load. The problem formulation considers an objective to reduce power loss of distribution systems and the constraints such as the number or total capacity of DGs and the deviation of the bus voltage. The main idea of solving fuzzy goal programming is to transform the original objective function and constraints into the equivalent multi-objectives functions with fuzzy sets to evaluate their imprecise nature for the criterion of power loss minimization, the number or total capacity of DGs and the bus voltage deviation, and then solve the problem using genetic algorithm. The method proposed is applied to IEEE 12 bus and 33 bus test systems to demonstrate its effectiveness. .

이중게이트 MOSFET의 채널구조에 따른 항복전압 변화 (Breakdown Voltages Deviation for Channel Dimension of Double Gate MOSFET)

  • 정학기
    • 한국정보통신학회논문지
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    • 제17권3호
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    • pp.672-677
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    • 2013
  • 본 연구에서는 이중게이트 MOSFET의 채널크기 변화에 따른 항복전압의 변화를 분석하였다. 차세대 나노소자인 DGMOSFET에 대한 단채널효과 중 매우 작은 값을 갖는 항복전압은 정확한 분석이 요구되고 있다. 항복전압분석을 위하여 포아송방정식의 분석학적 전위분포를 이용하였으며 이때 전하분포함수에 대하여 가우시안 함수를 사용함으로써 보다 실험값에 가깝게 해석하였다. 가우시안 함수의 변수인 이온주입범위 및 분포편차 그리고 소자 파라미터인 채널의 두께, 도핑농도 등에 대하여 항복전압 특성의 변화를 관찰하였다. 본 연구의 모델에 대한 타당성은 이미 기존에 발표된 논문에서 입증하였으며 본 연구에서는 이 모델을 이용하여 항복전압특성을 분석할 것이다. 분석결과 항복전압은 소자파라미터 및 가우시안분포함수의 모양에 크게 영향을 받는 것을 관찰할 수 있었다.

DGMOSFET의 채널구조에 따른 항복전압변화에 대한 분석 (Analysis of Breakdown Voltages Deviation for Channel Dimension of Double Gate MOSFET)

  • 정학기;한지형;정동수;이종인
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2012년도 추계학술대회
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    • pp.811-814
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    • 2012
  • 본 연구에서는 이중게이트 MOSFET의 채널크기 변화에 따른 항복전압의 변화를 분석할 것이다. 차세대 나노소자인 DGMOSFET에 대한 단채널효과 중 매우 작은 값을 갖는 항복전압은 정확한 분석이 요구되고 있다. 항복전압분석을 위하여 포아송방정식의 분석학적 전위분포를 이용하였으며 이때 전하분포함수에 대하여 가우시안 함수를 사용함으로써 보다 실험값에 가깝게 해석하였다. 가우시안 함수의 변수인 이온주입범위 및 분포편차 그리고 소자 파라미터인 채널의 두께, 도핑농도 등에 대하여 항복전압 특성의 변화를 관찰하였다. 본 연구의 모델에 대한 타당성은 이미 기존에 발표된 논문에서 입증하였으며 본 연구에서는 이 모델을 이용하여 항복전압특성을 분석할 것이다. 분석결과 항복전압은 소자파라미터 및 가우시안분포함수의 모양에 크게 영향을 받는 것을 관찰할 수 있었다.

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선간전압과 상전압에 대한 전압불평형율의 비교 (Comparison of Voltage Unbalance Factor for Line and Phase Voltage)

  • 김종겸;박영진;이은웅
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제54권9호
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    • pp.403-407
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    • 2005
  • Most of the loads in industrial power distribution systems are balanced and connected to three power systems. However, voltage unbalance is generated at the user's 3-phase 4-wire distribution systems with single & three phase. Voltage unbalance is mainly affected by load system rather than power system. Unbalanced voltage will draws a highly unbalanced current and results in the temperature rise and the low output characteristics at the machine. It is necessary to analyse correct voltage unbalance factor for reduction of side effects in the industrial sites. Voltage unbalance is usually defined by the maximum percent deviation of voltages from their average value, by the method of symmetric components or by the expression in a more user-friendly form which requires only the three line voltage readings. If the neutral point is moved by the unbalanced load at the 3-phase 4-wire system. Line and phase voltage unbalance leads to different results due to zero-sequence component. So that it is difficult to analyse voltage unbalance factor by the conventional analytical method, This paper presents a new analytical method for phase and line voltage unbalance factor in 4-wire systems. Two methods indicate exact results.

Display Driver IC용 Amplifier Input Transistor의 Matching 개선 (The Improvement of Matching of Amplifier Input Transistor for Display Driver IC)

  • 김현철;노용한
    • 한국전기전자재료학회논문지
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    • 제21권3호
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    • pp.213-216
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    • 2008
  • The voltages for pixel electrodes on LCD panels are supplied with analog voltages from LCD Driver ICs (LDIs). The latest LDI developed for large LCD TV's has suffered from the degradation of analog output characteristics (target voltage: AVO and output voltage deviation: dVO). By the failure analysis, humps in $I_D-V_G$ curves have been observed in high voltage (HV) NMOS devices for input transistors in amplifiers. The hump is investigated to be the main cause of the deviation for the driving current in HV NMOS transistors. It also makes the matching between two input transistors worse and consequently aggravates the analog output characteristics. By simply modifying the active layout of HV NMOS transistors, this hump was removed and the analog characteristics (AVO &dVO) were improved significantly. In the help of the improved analog characteristics, it also became possible to reduce the size of the input transistors less than a half of conventional transistors and significantly improve the integration density of LDIs.

반응표면분석법에 의한 적층 칩 바리스터의 전기적 특성 (Electrical Properties of Multilayer Chip Varistors in the Response Surface Analysis)

  • 윤중락;정태석;최근묵;이석원
    • 한국전기전자재료학회논문지
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    • 제20권6호
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    • pp.496-501
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    • 2007
  • In order to enhance sintering characteristics on the $ZnO-Pr_6O_{11}$ based multilayer chip varistors (MLVs), a response surface analysis using central composite design method were carried out. As a result, varistor voltage($V_{1mA}$), nonlinear coefficient ($\alpha$), leakage current ($I_L$) and capacitance (C) were considered to be mainly affected by sintered temperature and holding time. MLVs sintered at $1200^{\circ}C$ and above $1200^{\circ}C$ revealed poor electrical characteristics, possibly due to the reaction between electrode materials(Pd) and $ZnO-Pr_6O_{11}$ based ceramics. On the sintering temperature range $1150{\sim}1175^{\circ}C$, nonlinear coefficient ($\alpha$) and leakage current ($I_L$) were shown to be $60{\sim}69$ and below $0.3{\mu}A$, respectively. In particular, MLVs sintered at $1175^{\circ}C$, 1.5 hr and $2^{\circ}C/hr$ (cooling speed) showed stable ESD(Electrical Static Discharge) characteristics under the condition of 10 times at 8 Kv with deviation varistor voltage, and deviation nonlinear coefficient were 0.3% and 0.33% (at positive), 0.55% (at negative), respectively.

다중센서 신호특성 최적화를 통한 와전류검사 신뢰성 개선연구 (The Study on Reliability Improvement in Eddy Current Inspection by Signal Characteristic Optimization of Multi-coil Array Probe)

  • 안연식;길두송;박상기
    • 동력기계공학회지
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    • 제14권2호
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    • pp.60-64
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    • 2010
  • This paper introduces reliability improvement and time saving in eddy current inspection by signal characteristic optimization of multi-coil eddy current array probe. In the past, Multi-coil array probe and single probe were used for the gas turbine rotor surface inspection & defect evaluation. The multi-coil array probe was used for the broad area inspection. But the signal deviations among multi-coil array probe are maximum 28% in commercial probe. This differences were considered to impedance differences among coils, so it is very difficult to evaluate exact defect size. The signal deviations among multi-coil array probe are maximum 28% in commercial probe. So, single coil inspection was used for exact defect sizing. The purpose of this study is to improve signal deviations of multi-coil array probe. The introduced new technology can improves this deviation by adjusting input voltage in each coil. At first, apply same voltage in each coil and collect signal amplitude of each coil. And calculate new input voltage based on signal amplitude of each coil. If the signal amplitude deviation is within 5% among multi-coil array probe, the signal amplitude of multi-coil array probe is reliable. The proposed technology gives 2% signal deviation among multi-coil array probe. The proposed new technology gives reliability improvement and inspection time saving in eddy current inspection.

Glass 첨가량에 따른 ZnO 바리스터의 전기적 특성 (Electrical Properties of ZnO Varistors with Variation of Glass Addition)

  • 조현무;이종덕;박상만;이성갑
    • 한국전기전자재료학회논문지
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    • 제18권9호
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    • pp.815-820
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    • 2005
  • ZnO varistor ceramics were fabricated with variation of addition of glass-frit amount and the sintering temperature was $1100^{\circ}C$. The average grain sizes were showed increased from $8.6{\mu}m\;to\;10{\mu}m$, and varistor voltages were decreased from 506V to 460V by added amount of glass-frit. Nonlinear coefficient $\alpha$, of all were with increasing the amount of glass-frit more than 70, in case of added on $0.03wt\%$ glass-frit was 83. And leakage current were less than $1{\mu}A$ with applied at $82\%$ of varistor voltage. The clamping voltage ratio of the specimens added $0.03wt\%$ glass-frit was 1.41 at applied 25A $[8/20\;{\mu}s]$. In the specimen added $0.03wt\%$ glass-frit, endurance of surge current and deviation of varistor voltage were $6200A/cm^2,\;\Delta-1.67\%$, respectively and clamping voltage ratio was 2.33. In the Specimen added $0.03wt\%$ glass-frit were superior to any other compositions on High Temperature Load Test(HTLT) for 1000 hr at $85^{\circ}C$, and deviation of the varistor voltage were $\Delta-1.29\%$.