• 조명전기설비학회논문지
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• 제28권9호
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• pp.14-19
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• 2014

Recently, many renewable energy generating businesses are ongoing progress due to the introduction of the RPS(Renewable Portfolio Standards) as well as the needs of environmentally friendly energy resources. Researches on photovoltaic system are actively being processed since the photovoltaic system is relatively easy to install and becomes commercialized in many domestic application areas. Furthermore, the floating photovoltaic system is likely to be installed more actively since the conventional photovoltaic system requires relatively large areas of land. Also, the floating photovoltaic system is more efficient than photovoltaic system installed in land due to the operation in lower temperature. However, safety problems such as electric shock could arise since the cable should be installed in the water. In this paper, the leakage current and the voltage rising are measured and analyzed for the case when the cables are damaged connecting the floating photovoltaic system to the grid.

• ETRI Journal
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• 제38권1호
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• 전기전자학회논문지
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• 제23권2호
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• pp.552-556
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• 2019

본 논문에서는 전류 제어 회로를 이용하여 load Transient response 특성을 향상시킨 capless LDO(low drop-out) 레귤레이터를 제안하였다. LDO 레귤레이터 내부의 오차증폭기와 패스 트랜지스터 사이에 전류 조절 회로를 두어 전압 라인에 들어오는 전류특성을 개선시켜 기존의 LDO 레귤레이터보다 향상된 transient 응답특성을 갖는다. 제안된 회로는 cadence의 virtuoso, spectre 시뮬레이터를 이용하여 0.18 um 공정에서 특성을 분석하였다. 실험 결과에 따르면, 제안된 회로 구성을 이용한 LDO의 load transient response는 기존 LDO과 비교하여 부하 전류가 rising time인 경우 1.954 us에서 1.378 us, falling time인 경우 19.48 us에서 13.33 us으로 약 29%, 28% 개선된 응답속도를 가진다.

• 전기전자학회논문지
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• 제25권1호
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• pp.201-205
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• 2021

본 논문에서는 push-pull 감지 회로 구조로 인해 load transient 특성을 개선시킨 LDO를 제안하였다. LDO 레귤레이터 패스 트랜지스터의 입력단과 내부 오차증폭기의 출력단 사이에 제안된 push-pull 감지 회로 구조로 인한 전압 델타 값의 응답 특성을 개선시켜 종래의 LDO 레귤레이터보다 load transient 특성에서 우수한 효과를 가진다. 기존의 LDO 레귤레이터보다 rising time에서는 약 244 ns, falling time에서는 약 90 ns 만큼의 향상된 응답속도를 가진다. 제안된 회로는 Cadence사의 Spectre, Virtuoso 시뮬레이션 tool을 사용하여 samsung 0.13um 공정으로 특성 및 결과를 시뮬레이션 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.469-470
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• 2008

We have studied electro-optic characteristics as a function of splay elastic constants ($K_{11}$) in the fringe-field switching (FFS) mode using the LC with positive dielectric anisotropy. When $K_{11}$ is increased from 7.7pN to 11.7pN, a maximum transmittance is slightly increased and rising time become a little bit fast. However, operating voltage and threshold voltage is independent. In opposition to rising time, decay time is not affected by $K_{11}$. We already know that $K_{11}$ affects tilt angle of liquid crystals. Therefore, on the occasion of high $K_{11}$, liquid crystals are mainly affected by twist deformation because the higher $K_{11}$, the less tilt angle. In the FFS device, high $K_{11}$ is favorable to reduce tilt angle in on state and thus improve rising response time.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.234-238
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• 1999

In order to radiate X-ray, the low ripple stabilized high voltage DC over the range of 40KV to 150KV is directly inflicted to X-ray tube. The energy characteristics of the radiated X-ray depend on the pulsating waveforms of the DC voltage supplied X-ray tube. In general, the low ripple voltage waveforms with fast rising times are required to increase with the dosage per unit time lest the exposure time should be longer in orde that the motion artifacts of an object may be eliminated in actual. The conventional types of X-ray generators were bulky in physical size and heavy in weight, and the control accuracies of the output voltages were not always satisfactory. The high frequency switching inverter and converter technology on power conversion and control systems have been greatly closed up introducing new power semiconductor devices. To decreasing the volume and the weight of high voltage transformer, and to stabilize ripple, a high frequency PWM inverter is connected between DC source and high voltage transformer. This paper describes the output characteristics according to stabilize ripple of X-ray tube voltage and compared the reproducibility, direcibility and doesage.

• 대한전자공학회논문지SD
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• 제39권2호
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• pp.56-62
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• 2002

문턱전압 스윙 드라이버(threshold voltage swing driver)와 이중 감지 증폭기 리시버(dual sense amplifier receiver)를 가진 새로군 고속 저전압 스윙 온 칩 버스 (on-chip BUS)를 제안하였다. 문턱전압 스윙 드라이버는 버스에서의 전압상승 시간을 CMOS 인버터(inverter) 드라이버에서의 약 30% 이내로 줄여주고, 이중 감지 증폭기 리시버는 감지 증폭기 리시버를 사용하는 기존의 저전압 스윙 버스들의 데이터 전송량을 두 배 향상시켜 준다. 문턱전압 스윙 드라이버와 이중 감지 증폭기 리시버를 모두 사용할 경우, 온 칩 버스에서 사용하는 기존의 CMOS 인버터와 비교하여 제안된 방식은 약 60%의 속도 증가와 75%의 소모전력 감소를 얻는다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.14-21
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• 2009

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a $0.18{\mu}m$ CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a $0.18{\mu}m$ CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.815-818
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• 1998

The Insulated Gate Bipolar Transistor has the characteristics of MOSFET and BJT. The characteristics of proposed device exhibit high speed switching, the voltage controlled property, and the low ON resistance. This hybrid device has been used and developed continuously in the power electronic engineering field. We can simulate many IGBT circuits, such as the motor drive circuit, the switching circuits etc, with PSpice. However, some problems in PSpice is that the IGBT is old-fashioned and is very difficult to get it. In this paper, the IGBT in PSpice is considered as the basic structure. We changed the valuse of base width, gate-drain overlaping area, device area, and doping concentration, then calculated MOS transconductance, ambipolar recombination lifetime etc. Using this resultant parameter, we could predict the transient response characteristicsof IGBT, for examplex, voltage overshoot, the rising curve of voltage, and the falling curve of current.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.264-268
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• 2003

This paper describes a high voltage high power DC power supply which has the ability of pulsed mode operation. The power supply Is constructed with several series connected power converters based on modified multilevel converters. The modified multilevel converters are suitable for the protection of frequent output short-circuit. The output dc power of the proposed converter can be disconnected from the load within several hundred microseconds at the instant of short-circuit fault. The rising time of the dc load voltage is as small as several hundred microseconds, and there is no overshoot of the do voltage because the dc output capacitors keep undischarged state. Analysis, simulations, and experiments are carried out to Investigate the operation and usefulness of the proposed scheme.