• Journal of the Korean Applied Science and Technology
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• v.41 no.1
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• pp.46-57
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• 2024

In this study, the various process conditions for high-power DC Magnetron Sputtering (DCMS) on the surface roughness of carbon thin films were investigated. The optimal conditions for Si/C coating were 40min for deposition time, which does not deviate from normal plasma, to obtain the maximum deposition rate, and the conditions for the best surface roughness were -16volt bias voltage and 400watt DC power with 1.3x10-3torr chamber pressure. Under these optimal conditions, an excellent carbon thin film with a surface roughness of 1.62nm and a thickness of 724nm was obtained. As a result of XPS analysis, it was confirmed that the GLC structure (sp² bonding) was more dominant than the DLC structure (sp³ bonding) in the thin film structure of the carbon composite layer formed by DC sputtering. Except in infrequent cases of relatively plasma instability, the lower bias voltage and applied power induces smaller surface roughness value due to the cooling effect and particle densification. For the optimal conditions for Graphite/C composite layer coating, a roughness of 36.3 nm and a thickness of 711 nm was obtained under the same conditions of the optimal process conditions for Si/C coating. This layer showed a immensely low roughness value compared to the roughness of bare graphite of 242 nm which verifies that carbon coating using DC sputtering is highly effective in modifying the surface of graphite molds for glass forming.

• Advances in nano research
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• v.9 no.3
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• pp.133-145
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• 2020

In this study, nonlinear vibrations and dynamic instabilities of a smart embedded micro shell conveying varied fluid flow and subjected to the combined electro-thermo-mechanical loadings are investigated. With the aim of designing new hydraulic sensors and actuators, the piezoelectric materials are employed for the body and the effects of applying electric field on the stability of the system as well as the induced voltage due to the dynamic behavior of the system are studied. The nonlocal piezoelasticity theory and the nonlinear cylindrical shell model in conjunction with the energy approach are utilized to mathematically modeling of the structure. The fluid flow is assumed to be isentropic, incompressible and fully develop, and for more generality of the problem both steady and time dependent flow regimes are considered. The mathematical modeling of fluid flow is also carried out based on a scalar potential function, time mean Navier-Stokes equations and the theory of slip boundary condition. Employing the modified Lagrange equations for open systems, the nonlinear coupled governing equations of motion are achieved and solved via the state space problem; forth order numerical integration and Bolotin's method. In the numerical results, a comprehensive discussion is made on the dynamical instabilities of the system (such as divergence, flutter and parametric resonance). We found that applying positive electric potential field will improve the stability of the system as an actuator or vibration amplitude controller in the micro electro mechanical systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.682-687
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• 2014

We have performed reverse gate bias stress tests on AlGaN/GaN-on-Si Heterostructure FETs (HFETs). The shift of threshold voltage ($V_{th}$) and the reduction of on-current were observed from the stressed devices. These changes of the device parameters were not permanent. We investigated the temporary behavior of the stressed devices by analyzing the temperature dependence of the instabilities and TCAD simulation. As the baseline temperature of the electrical stress tests increased, the changes of the $V_{th}$ and the on-current were decreased. The on-current reduction was caused by the positive shift of the $V_{th}$ and the increased resistance of the gate-to-source and the gate-to-drain access region. Our experimental results suggest that electron-trapping effect into the shallow traps in devices is the main cause of observed instabilities.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.471-474
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• 2004

We investigated field emission (FE) characteristics of multi-walled carbon nanotubes (CNTs) grown on all over patterned cathode electrode lines (CL pattern) and grown on along the central areas of the cathode lines(CL pattern). The CNTs grown on the SL pattern showed a lower threshold voltage and higher emission current than those on the CL pattern, due to the concentration of electric fields at the edges of the cathode lines. For the SL-patterned CNTs, however, the FE gradually spread out to the neighbors with time, and was instantly extinguished in some area and then slowly resumed again. Such areal- spread FE did not occur for the CL-patterned sample, leading to the stable FE together with the instant turn-on capability. It is suggested that the spread FE and instability for the SL-patterned CNTs may be related to the electrical charging on the insulator surface around the cathode line edges.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.32 no.3
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• pp.232-239
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• 2008

The position sensors used in a magnetic bearing system are desirable to provide some degree of fault-tolerance as the rotor position is necessary for the feedback control to overcome the open-loop instability. In this paper, we propose an inductive position sensor that can cope with a partial fault in the sensor. The sensor has multiple poles which can be combined to sense the in-plane motion of the rotor. When a high-frequency voltage signal drives each pole of the sensor, the resulting current in the sensor coil contains information regarding the rotor position. The signal processing circuit of the sensor extracts this position information. In this paper, we used the magnetic circuit model of the sensor that shows the analytical relationship between the sensor output and the rotor motion. The multi-polar structure of the sensor makes it possible to introduce redundancy which can be exploited for fault-tolerant operation. The proposed sensor is applied to a magnetically levitated turbo-molecular vacuum pump. Experimental results validate the fault-tolerance algorithm.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• Journal of Power Electronics
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• v.9 no.3
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• pp.447-455
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• 2009

The power supply systems, which require low-voltage / high-current output has been changing from the conventional centralized power system to a distributed power system. The distributed power system consists of a bus converter and POL. The most important factor is the system stability in bus architecture design. The overlap between the output impedance of a bus converter input impedance of POL causes system instability and has been an actual problem. By increasing the bus capacitor, the system stability can be easily improved. However, due to limited space on the system board, the increasing of bus capacitors is impractical. An urgent solution of this issue is strongly desired. This paper presents the output impedance design for on-board distributed power system by means of three control schemes of a bus converter. The output impedance peak of the bus converter and the input impedance of the POL are analyzed and then conformed experimentally for stability criterion. Furthermore, the design process of each control schemes for system stability is proposed.

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.551-553
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• 2002

The cubicle type GIS rated at 25.8kV has been designed and manufactured by Jinkwang E&C eacently with their own technologies and KERI's assistances. The C-GIS has been tested to check the design capability for reference before conducting the type test. The operating characteristics test, short time withstand current and peak withstand current test, basic short circuit test duty T60 for preconditioning test, cable charging current switching test, capacitor bank current switching test, basic short circuit test duty T100s and T100a, single phase earth fault test, double earth fault test has been conducted. The test results show that the design and the manufacturing of the C-GIS has an enough capability to pass through the type test except the occurrence of 2 NSDDs in the cable charging current switching test and the instability of opening time at the minimum operating voltage. The problems shown in the tests will be improved soon and the successful pass will be expected in the following type test.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.876-881
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• 2011

The sintering, defect and grain boundary characteristics of Bi-based ZnO chip varistor (1,608 mm size) have been investigated to know the possibility of lowering a manufacturing price by using 100 % Ag inner-electrode. The samples were prepared by general multilayer chip varistor process and characterized by shrinkage, SEM, current-voltage (I-V), admittance spectroscopy (AS), impedance and modulus spectroscopy (IS & MS) measurement. There are no problems to make a chip varistor with 100% Ag inner-electrode in the sintering temperature range of 850~900$^{\circ}C$ for 1 h in air. A good varistor characteristics ($V_n$= 9.3~15.4 V, a= 23~24, $I_L$= 1.0~1.6 ${\mu}A$) were revealed but formed $Zn_i^{{\cdot}{\cdot}}$(0.209 eV) as dominant defect, and increased the distributional inhomogeneity and the temperature instability in grain boundary barriers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.166-173
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• 2009

The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.