• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.10-15
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• 2021

Cache bypassing schemes have been studied to remove unnecessary updating the data in cache blocks. Among them, a statistics-based cache bypassing method for asymmetric-access caches is one of the most efficient approach for non-voliatile memories and shows the lowest cache access latency. However, it is proposed under the condition of the normal cache system, so further study is required for the hybrid cache architecture. This paper proposes a novel cache bypassing scheme, called hybrid bypassing block selector. In the proposal, the new model is established considering the SRAM region and the non-volatile memory region separately. Based on the model, hybrid bypassing decision block is implemented. Experiments show that the hybrid bypassing decision block saves overall energy consumption by 21.5%.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.2
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• pp.94-101
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• 2008

Non-volatile RAM (NVRAM) is a form of next-generation memory that has both characteristics of nonvolatility and byte addressability each of which can be found in nonvolatile storage and RAM, respectively. The advent of NVRAM may possibly bring about drastic changes to the system software landscape. When NVRAM is efficiently exploited in the system software layer, we expect that the system performance can be significantly improved. In this regards, we attempt to develop a new Flash file system, named MiNVFS (Metadata in NVram File System). MiNVFS maintains all the metadata in NVRAM, while storing all file data in Flash memory. In this paper, we present quantitative experimental results that show how much performance gains can be possible by exploiting NVRAM. Compared to YAFFS, a typical Flash file system, we show that MiNVFS requires only minimal time for mounting. MiNVFS outperforms YAFFS by an average of around 400% in terms of the total execution time for the realistic workloads that we considered.

• Journal of IKEEE
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• v.23 no.1
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• pp.80-90
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• 2019

Even though Non-Volatile Memory (NVM) is used for data storage, a page table should be built to access data in it. And this observation leads us to the Persistent Page Table (PPT) scheme that keeps the page table in NVM persistently. By the way, processors have different page table structures and really operational page table cannot be built without virtual and physical addresses of NVM. However, those addresses are determined dynamically when NVM storage is attached to the system. Thus, the PPT should have system-independent and also address-independent structure and really working system-dependent page table should be built from the PPT. Moreover, entries of PPT should be updated atomically and, in this paper, we describe the design of PPT that meets those requirements. And we investigate how file systems can decrease the journaling overhead with the swap operation, which is a new operation created by the PPT. We modified the Ext4 file system in Linux and experiments conducted with Filebench workloads show that the swap operation enhances file system performance up to 60%.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.20.1-20.1
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• 2011

The nano-sized quantum structure has been an attractive candidate for investigations of the fundamental physical properties and potential applications of next-generation electronic devices. Metal nano-particles form deep quantum wells between control and tunnel oxides due to a difference in work functions. The charge storage capacity of nanoparticles has led to their use in the development of nano-floating gate memory (NFGM) devices. When compared with conventional floating gate memory devices, NFGM devices offer a number of advantages that have attracted a great deal of attention: a greater inherent scalability, better endurance, a faster write/erase speed, and more processes that are compatible with conventional silicon processes. To improve the performance of NFGM, metal nanocrystals such as Au, Ag, Ni Pt, and W have been proposed due to superior density, a strong coupling with the conduction channel, a wide range of work function selectivity, and a small energy perturbation. In the present study, bismuth metal nanocrystals were self-assembled within high-k $Bi_2Mg_{2/3}Nb_{4/3}O_7$ (BMN) films grown at room temperature in Ar ambient via radio-frequency magnetron sputtering. The work function of the bismuth metal nanocrystals (4.34 eV) was important for nanocrystal-based nonvolatile memory (NVM) applications. If transparent NFGM devices can be integrated with transparent solar cells, non-volatile memory fields will open a new platform for flexible electron devices.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.651-660
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• 2008

Flash memory is widely used in embedded systems because of its benefits such as non-volatile, shock resistant, and low power consumption. However, NAND flash memory suffers from out-place-update, limited erase cycles, and page based read/write operations. To solve these problems, YAFFS and RFFS, the flash memory file systems, are proposed. However YAFFS takes long time to mount the file system, because all the files are scattered all around flash memory. Thus YAFFS needs to fully scan the flash memory. To provide fast mounting, RFFS has been proposed. It stores all the block information, the addresses of block information and meta data to use them at mounting time. However additional operations for the meta data management are decreasing the performance of the system. This paper presents a new NAND flash file system called ERFFS (Efficient and Reliable Flash File System) which provides fast mounting and recovery with minimum mata data management. Based on the experimental results, ERFFS reduces the flash mount/recovery time and the file system overhead.

• Journal of KIISE
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• v.42 no.11
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• pp.1314-1321
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• 2015

Mobile devices employ buffer cache mechanisms, just as in computer systems such as desktops or servers, to mitigate the performance gap between main memory and secondary storage. However, DRAM has a problem in that it accelerates battery consumption by performing refresh operations periodically to maintain the stored data. In this paper, we propose a novel buffer cache scheme to increase the battery lifecycle in mobile devices based on a hybrid main memory architecture consisting of DRAM and non-volatile PCM. We also suggest a new buffer cache policy that allocates buffers based on process states to optimize the performance and endurance of PCM. In particular, our algorithm allocates each page to the appropriate position corresponding to the state of the application that owns the page, and tries to ensure a rapid response of foreground applications even with a small amount of DRAM memory. The experimental results indicate that the proposed scheme reduces the elapsed time of foreground applications by 58% on average and power consumption by 23% on average without negatively impacting the performance of background applications.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.237-237
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• 2006

P(VDF/TrFE(72/28) ultrathin films were used in the fabrication of Metal-Ferroelectric polymer-Metal (MFM) single bit device with special emphasis on uniform film surface, faster dipole switching time under applied external field and longer memory retention time. AFM and FTIR-GIRAS were complementary in analyzing surface crystalline morphology and the resultant change in chain orientation with varying thermal history. DC-EFM technique was used to 'write-read-erase' the data on the memory bit in a much faster time than P-E studies. The results obtained from this study will enable us to have a good understanding of the ferroelectric and piezoelectric behavior of P(VDF/TrFE)(72/28) thin films suitable for high density data storage applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.135-135
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• 2011

최근, 아이팟, 아이패드, 스마트폰 등의 휴대정보 기기의 수요가 급격히 증가하면서, 고집적성(테라비트급), 초소형, 초고속성, 고신뢰성을 확보할 수 있는 나노스케일(nano-scale)의 비휘발성 메모리(Non-volatile Memory; NVM) 소자 개발에 많은 연구가 집중되고 있다. 현재, 기존 CMOS 반도체 공정과 호환성이 우수하면서 고집적성의 특성이 가능한 전하트랩 플래시(Chrage Trap Flash : CTF) 메모리 소자가 차세대 비휘발성 메모리로써 각광 받고 있다. 하지만, 이러한 CTF 소자가 32 nm 이하로 스케일 다운이 되면서, ONO 층의 크기와 두께가 상당히 작고 얇아짐에 따라, 메모리 트랩수가 상당히 줄어들기 때문에 프로그램/소거 상태를 인지하는 메모리 윈도우의 마진을 확보하는데 어려움이 있다. 본 논문에서는 500 nm 크기를 갖는 폴리스티렌 비드(bead)를 이용한 나노 리소그래피 공정으로 질화막 표면에 roughness를 주어, 질화막과 블로킹 산화막의 경계면에 메모리 트랩의 표면적이 증가시켜, 메모리 윈도우 증가와 프로그램 속도를 개선을 구현하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.3
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• pp.200-205
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• 2000

This paper describes the structure modeling and operation characteristics of MFMIS(metal-ferroelectric-metal-insulator-semiconductor) device using the Tsuprem4 which is a semiconductor device tool by Avanti. MFMIS device is being studied for nonvolatile memory application at various semiconductor laboratory but it is difficult to fabricate and analyze MFMIS devices using the semiconductor simulation tool: Tsuprem4, medici and etc. So the new library and new materials parameters for adjusting ferroelectric material and platinum electrodes in the tools are studied. In this paper structural model and operation characteristics of MFMIS devices are measured, which can be easily adopted to analysis of MFMIS device for nonvolatile memory device application.

• Bulletin of the Korean Space Science Society
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• 2010.04a
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• pp.31.1-31.1
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• 2010

On-Orbit상에서 인공위성의 탑재소프트웨어를 교정하는 경우는 크게 위성의 하드웨어 문제를 소프트웨어적으로 해결/완화, 임무 중 소프트웨어 기능 향상 그리고 지상테스트 동안 확인되지 못한 소프트웨어 문제를 수정하기 위해서 사용된다. 탑재소프트웨어 설계과정에서 이러한 요구조건을 만족할 수 있도록 탑재소프트웨어가 설계되어야 하며 소프트웨어 교정을 위한 잉여 메모리를 반드시 할당해야 한다. 또한, 탑재소프트웨어 실행파일 생성할 경우에도 각 섹션별로 패치가 가능하도록 메모리 맵을 생성해야한다. 기존 저궤도 위성에서는 휘발성 메모리인 RAM 영역에 한해서만 탑재소프트웨어 교정이 가능하였으나 현재 개발 중인 차세대 저궤도 위성에서는 비휘발성 메모리 영역 즉 SGM(Safe Guard Memory)와 NVMEM(Non-Volatile Memory)을 이용하여 탑재소프트웨어를 교정할 수 있는 방식을 제공하고 있다. 이 논문에서는 차세대 저궤도 위성의 탑재소프트웨어의 실시간 교정을 위한 탑재소프트웨어 아키텍처와 제한 사항에 대해서 설명하며 실제 탑재소프트웨어를 교정 하는 방안 과 절차에 대하여 설명한다.