• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.657-660
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• 2011

Differential detection algorithm for DBO-CSS based on maximum signal energy detection (MSED) using viterbi algorithm is proposed. In order to mitigate SNR degradation caused by differential decoding, a modified viterbi algorithm with so called correlation metric (CM) in every state is proposed. It is shown that the performance gain of the proposed algorithm when compared with that of the conventional differential detection with the block decoding algorithm is about 2.5dB at BER = $10^{-5}$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.100-110
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• 1994

This paper proposes an efficient traceback method for parallel hardware implementation of the Viterbi algorithm. Compared to the conventional Viterbi algorithm where initial state for traceback is selected arbitrarily the proposed algorithm decides decoding output by analyzing the survivor paths of consecutive tracebacks. This makes Viterbi algorithm more efficient in error correction event when more than one survivor path exists. The proposed traceback algorithm together with its hardware realization is presented in this paper. Experimental results show tht the proposed algorithms is efficient in error correction in noisy channels compared to the existing algorithms.

• The Journal of the Acoustical Society of Korea
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• v.26 no.1E
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• pp.21-26
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• 2007

In this paper, we propose a modified Viterbi algorithm to compensate for endpoint detection error during the decoding phase of an isolated word recognition task. Since the conventional Viterbi algorithm explores only the search space whose boundaries are fixed to the endpoints of the segmented utterance by the endpoint detector, the recognition performance is highly dependent on the accuracy level of endpoint detection. Inaccurately segmented word boundaries lead directly to recognition error. In order to relax the degradation of recognition accuracy due to endpoint detection error, we describe an unconstrained search of word boundaries and present an algorithm to explore the search space with efficiency. The proposed algorithm was evaluated by performing a variety of simulated endpoint detection error cases on an isolated word recognition task. The proposed algorithm reduced the Word Error Rate (WER) considerably, from 84.4% to 10.6%, while consuming only a little more computation power.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.646-649
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• 2011

Differential detection algorithm for DBO-CSS based on maximum signal energy detection (MSED) using viterbi algorithm is proposed. In order to mitigate SNR degradation caused by differential decoding, a modified viterbi algorithm with so called correlation metric (CM) in every state is proposed. It is shown that the performance gain of the proposed algorithm when compared with that of the conventional differential detection with the block decoding algorithm is about 2.5dB at BER = $10^{-5}$.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.663-666
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• 2004

In this paper, a modified-SOYA (soft output viterbi algorithm) of turbo codes is proposed for quantized channel receiver filter outputs. We derive optimum branch values for the Viterbi algorithm. Here we assume that received filter outputs are quantized and the channel is additive white Gaussian noise. The optimum non-uniform quantizer is used to quantize channel receiver filter outputs. To compare the BER (bit error rate) performance we perform simulations for the modified SOYA algorithm and the general SOYA

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.61-66
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• 2001

In this paper, we design high speed Viterbi decoding algorithm which is aimed for Wireless LAN. Wireless LAN transmits data at rate 6∼54 Mbps. This high speed is not easy to implement Viterbi decoder with single ACS. So parallel ACS butterfly structure is to be used and several time-dependent problem is to be solved. We simulate Viterbi algorithm using new branch metric calculating method to save time, and consider trace back algorithm which is adaptable to high speed Viterbi decoder. With simulated, we determine the structure of Viterbi decoder. This architecture is available to high speed and low power Viterbi decoder.

• The Journal of the Acoustical Society of Korea
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• v.21 no.2
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• pp.190-198
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• 2002

In general, we have used the Viterbi algorithm of Speech recognition for decoding. But a decoder in speaker verification has to recognize same word of every speaker differently. In this paper, we propose a noble decoding algorithm that could replace the typical Viterbi algorithm for the speaker verification system. We utilize for the proposed algorithm the speaker adaptation algorithms that transform feature vectors into the region of the client' characteristics in the speech recognition. There are many adaptation algorithms, but we take MLLR (Maximum Likelihood Linear Regression) and MAP (Maximum A-Posterior) adaptation algorithms for proposed algorithm. We could achieve improvement of performance about 30% of EER (Equal Error Rate) using proposed algorithm instead of the typical Viterbi algorithm.

• Journal of IKEEE
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• v.24 no.3
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• pp.838-844
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• 2020

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.53-61
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• 2002

This paper proposes new DSP instructions and their architecture which efficiently implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecutre can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1923-1931
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• 2000

In this paper, e analyze the performance of the PSS-type Viterbi decoder which can reduce calculations and power consumption using the Monte Carlo simulations. Gaussian and burst noise channels are considered in this simulation, and we achieve that convolutional interleaver can reduce complexity and power consumption in burst noise channel. In order to implement the high-speed PSS-type Viterbi decoder, the architectures of decoder are presented, and we implemented the PSS-type Viterbi decoder for r=1/2, k=3 using the VHDL tool, and prove the decoding process.