• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.29-36
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• 2005

This paper presents the first hardware design of ARIA that KSA(Korea Standards Association) decided as the block encryption standard at Dec. 2004. The ARIA cryptographic algorithm has an efficient involution SPN (Substitution Permutation Network) and is immune to known attacks. The proposed ARIA design based on 1 cycle/round include a dual port ROM to reduce a size of circuit md a high speed round key generator with barrel rotator. ARIA design proposed is implemented with Xilinx VirtexE-1600 FPGA. Throughput is 437 Mbps using 1,491 slices and 16 RAM blocks. To demonstrate the ARIA system operation, we developed a security system cyphering video data of communication though Internet. ARIA addresses applications with high-throughput like data storage and internet security protocol (IPSec and TLS) as well as IC cards.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.6
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• pp.2999-3004
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• 2013

Smartphone subscribers exceeded 30 million people, Smart Korea is up on this track, and leaping to 'Smart powerful nation from 'IT powerful nation. Of course, the popularization of the smart phone called 'PC in the hands' has brought a revolutionary change to nation livelihood, and also to business and government, too. The current usage of Smartphone is not just a simple function call, people can communicate anytime, anywhere with it. The current usage of Smartphone is not just a simple function call, people can communicate anytime, anywhere with it. And it has become the culture of the terminal type in the hands whenever and wherever. However, the screen size and the existing flash or video files do not run when trying to access to the homepage for PC with Smartphone. and it may gives the inconvenience to people who use mobile devices. Therefore, in this paper, it is a study for the provision of an efficient service for Smartphone users through the establishment of website for mobile in mobile circumstances.

• Journal of Broadcast Engineering
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• v.8 no.1
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• pp.63-71
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• 2003

In sport programs, real-time virtual imaging system come into notice for new technology which can compose information like team logos, scores. distances directly on playing ground, so it can compensate for the defects of general character generator. In order to synchronize graphics to camera movements, generally two method is used. One is for using sensors attached to camera moving axis and the other is for analyzing camera video itself. KBS technical research institute developed real-time sensor-based virtual imaging system 'VIVA', which uses four sensors on pan, tilt, zoom, focus axis and controls virtual graphic camera in three dimensional coordinates in real-time. In this paper, we introduce our system 'VIVA' and it's technology. For accurate camera tracking we calculated view-point movement occurred by zooming based on optical principal point variation data and we considered field of view variation not only by zoom but also by focus. We developed our system based on three dimensional graphic environment. so many useful three dimensional graphic techniques such as keyframe animation can be used. VIVA was successfully used both in Busan Asian Games and 2002 presidential election. We confirmed that it can be used not only in the field but also in the studio programs in which camera is used within more close range.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1507-1518
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• 2020

High-quality images have a lot of information, so sensitive data is stored by encryption for private company, military etc. Encrypted images can only be decrypted with a secret key, but the original data cannot be retained when attacked by the Shear attack and Noise pollution attack techniques that overwrite some pixel data with arbitrary values. Important data is the more necessary a countermeasure for the recovery method against attack. In this paper, we propose a random number generator PingPong256 and a shuffling method that rearranges pixels to resist Shear attack and Noise pollution attack techniques so that image and video encryption can be performed more quickly. Next, the proposed PingPong256 was examined with SP800-22, tested for immunity to various noises, and verified whether the image to which the shuffling method was applied satisfies the Anti-shear attack and the Anti-noise pollution attack.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Journal of radiological science and technology
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• v.37 no.1
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• pp.7-14
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• 2014

By using a Chest Phantom(DUKE Phantom) focusing on dose reduction of diagnostic radiation field with the most use of artificial radiation, and attempt to reduce radiation dose studies technical radiation. Publisher of the main user of the X-ray Radiological technologists, Examine the effect of reducing the radiation dose to apply additional filtering of the X-ray generator. In order to understand the organ dose and effective dose by using the PC-Based Monte Carlo Program(PCXMC) Program, the patient receives, was carried out this research. In this experiment, by applying a complex filter using a copper and Al(aluminum,13) and filtered single of using only aluminum with the condition set, and measures the number of the disk of copper indicated by DUKE Phantom. The combination of the composite filtration and filtration of a single number of the disk of the copper is the same, with the PCXMC 2.0. Program looking combination of additional filtration fewest absorbed dose was calculated effective dose and organ dose. Although depends on the use mAs, The 80 kVp AP projection conditions, it is possible to reduce the effective amount of about 84 % from about 30 % to a maximum at least. The 120 kVp PA projection conditions, it is possible to reduce the effective amount of about 71 % from about 41 % to a maximum of at least. The organ dose, dose reduction rate was different in each organ, but it showed a decrease of dose rate of 30 % to up 100 % at least. Additional filtration was used on the imaging conditions throughout the study. There was no change in terms of video quality at low doses. It was found that using the DUKE Phantom and PCXMC 2.0 Program were suitable to calculate the effect of reducing the effective dose and organ dose.

• Korean Security Journal
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• no.30
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• pp.33-60
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• 2012

False alarm of Electronic security causes various serious side effects such as decrease of electronic security guard's morale caused by unnecessary mobilization, increase of fatigue caused by workload increase, increase of electronic security company owner's management burden and decrease of electronic security service utilization rate caused by customer's distrust. Therefore, the study considered the Korean regulation related with false alarm of electronic security and proposed actual status of false alarm and measure for it. The study proposed systematic resolution assignments and political assignments in relation with the measure for false alarm. Systematic resolution assignments are as follows. First, electronic security company should construct electronic security system accurately from the initial step of security consulting and security planning related with target facility. Second, it is necessary to encourage installation and operation of video monitoring system. Third, sensor wiring should be separated. Fourth, the measures for false alarm depending on main system causes should be prepared. It is necessary to encourage the installation of 'arming disarming alarm sound' generator. In addition, the measures for false arm depending on the characteristics of sensor should be prepared and standardized. Fifth, system maintenance should be reinforced. Political assignments related with the measures for false alarm are as follows. First, it is necessary to reinforce education & training. Individual nurturing & education process should be run by electronic security company or the education focusing on the measure for false alarm should be performed in job training defined in "Security Industry Act". Second, it is necessary to establish and reinforce legal regulation and establish device. If police authority standardizes the documents related with false alarm, provides their forms and requires them for periodical reports or documents, it is expected that good measures for false alarm will be prepared on the basis of actual data in the future. Third, cooperation organization to discuss the measures for false alarm like 'Conference for False Alarm of Electronic Security' should be organized and operated. Fourth, interest and role of electronic security company and electronic security supervisor should be enlarged.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.