• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.16-22
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• 1993

A via-hole process for reproducible and reliable GaAs MMIC fabrication is described. The via-hole etching process consists of two step dry etching. During the first etching step a BC $I_{3}$/C $I_{2}$/Ar gas mixure is used to achieve high etch rate and small lateral etching. In the second etching step. CC $L_{2}$ $F_{2}$ gas is used to achieve selective etching of the GaAs substrate with respect to the front side metal layer. Via holes are formed from the backside of a 100$\mu$m thick GaAs substrate that has been evaporated initially with 500.angs. thick chromium and subsequently a 2000.angs. thick gold layer. The fabricated via holes are electroplated with gold (~20$\mu$m thick) to form via connections. The results show that established via-hole process is satisfactory for GaAs MMIC fabrication.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.6
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• pp.236-243
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• 2004

The oxide etching process was characterized in a magnetically enhanced reactive ion etching (MERIE) reactor with a $CHF_3CF_4$ gas chemistry. A statistical experimental design plus one center point was used to characterize relationships between process factors and etch response. The etch response modeled are etch rate, etch selectivity to TiN and uniformity. Etching uniformity was improved with increasing $CF_4$ flow ratio, increasing source power, and increasing pressure depending on source power. Characterization of via etching in $CHF_3CF_4$ MERIE using neural networks was successfully executed giving to highly valuable information about etching mechanism and optimum etching condition. It was found that etching uniformity was closely related to surface polymerization, DC bias, TiN and uniformity.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.19-23
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• 2012

Silicon substrate for light emitting diodes (LEDs) has been the tendency of LED packaging for improving power consumption and light output. In this study, a low cost and high throughput Si through via fabrication has been demonstrated using a wet etching process. Both a wet etching only process and a combination of wet etching and dry etching process were evaluated. The silicon substrate with Si through via fabricated by KOH wet etching showed a good electrical resistance (${\sim}5.5{\Omega}$) of Cu interconnection and a suitable thermal resistance (4 K/W) compared to AlN ceramic substrate.

• Journal of the Semiconductor & Display Technology
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• v.2 no.3
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• pp.7-11
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• 2003

In this research, the etching characteristics of via contact and deep contact hole have been studied using multi-pole inductively coupled plasma(MICP) etching system. We investigated Plasma density of MICP source using the Langmuir probe and etching characteristics with RF frequency, wall temperature, chamber gap, and gas chemistry containing Carbon and Fluorine. As the etching time increases, formation of the polymer increases. To improve the polymer formation, we controlled the temperature of the reacting chamber, and we found that temperature of the chamber was very effective to decrease the polymer thickness. The deep contact etch profile and high selectivity(oxide to photoresist) have been achieved with the optimum mixed gas ratio containing C and F and the temperature control of the etching chamber.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.51-56
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• 2012

In order to fabricate through-Si-vias for thermal vias by using wet etching process, anisotropic etching behavior of Si substrate was investigated as functions of concentration and temperature of TMAH solution in this study. The etching rate of 5 wt%, 10 wt%, and 25 wt% TMAH solutions, of which temperature was maintained at $80^{\circ}C$, was $0.76{\mu}m/min$, $0.75{\mu}m/min$, and $0.30{\mu}m/min$, respectively. With changing the temperature of 10 wt% TMAH solution to $20^{\circ}C$ and $50^{\circ}C$, the etching rate was reduced to $0.067{\mu}m/min$ and $0.233{\mu}m/min$, respectively. Through-Si-vias of $500{\mu}m$-depth could be fabricated by etching a Si substrate for 5 hours in 10 wt% TMAH solution at $80^{\circ}C$ after forming same via-pattern on each side of the Si substrate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.31-38
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• 2002

In order to improve the 0.35 $mutextrm{m}$-via hole etching process the etching characteristic of the gas $C_2F_{6}$ has been analyzed. The samples were triple-layer films(TEOS/SOG/TEOS) on 8-inch wafers and the orthogonal array matrix technique was used for the process. The equipment for etching was the transformer coupled plasma (TCP) source which is a type of high density plasma(HDP). This experiment showed the etching rate for $C_2F_{6}$ was 0.8 $mutextrm{m}$/min-1.1 $mutextrm{m}$/min and the measured uniformity was under $pm$6.9% in the matrix window. The CD skew comparison between pre and post-etching was under 10% which is an outstanding results in the window of profile in anisotropic etching. There was no problem in C2F6 with the flow rate of 20sccm, but when 14sccm of $C_2F_{6}$ was supplied there was a recess problem on the inner wall of SOG film. Consequently the etching characteristic of $C_2F_{6}$ shows a fast etching rate and a very wide process window in HDP TCP.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.244-250
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• 2008

An inductively coupled plasma etching process to replace an existing slower rate reactive ion etching process for $60{\mu}m$ diameter via-holes using Cl2/BCl3 gases has been investigated. Process pressure and platen power were varied at a constant ICP coil power to reproduce the RIE etched $200{\mu}m$ deep via profile, at high etch rate. Desired etch profile was obtained at 40 m Torr pressure, 950 W coil power, 90W platen power with an etch rate ${\sim}4{\mu}m$/min and via etch yield >90% over a 3-inch wafer, using $24{\mu}m$ thick photoresist mask. The etch uniformity and reproducibility obtained for the process were better than 4%. The metallized via-hole dc resistance measured was ${\sim}0.5{\Omega}$ and via inductance value measured was $\sim$83 pH.

• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.187-190
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• 2005

High aspect ratio via-hole etching process has emerged as one of the most crucial means to increase component density for ULSI devices. Because of charge accumulation in via-hole, this sophisticated and important process still hold several problems, such as etching stop and loading effects during fabrication of integrated circuits. Indeed, the concern actually depends on accumulated charge. For monitoring accumulated charge during plasma etching process, charge-up monitoring sensor was fabricated and tested under some plasma conditions. This paper presents a neural network-based technique for analyzing and modeling several electrical performance of plasma charge-up monitoring sensor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.303-306
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• 2005

High aspect ration via-hole etching process has emerged as one of the most crucial means to increase component density for ULSI devices. Because of charge accumulation in via hole, this sophisticated and important process still hold several problems, such as etching stop, loading effects during fabrication of integrated circuits. Indeed, the concern actually depends on accumulated charge. For monitoring accumulated charge during plasma etching process, charge-up monitoring sensor was fabricated and tested under some plasma conditions. This paper presents a neural network-based technique for analyzing and modeling several electrical performance of plasma charge-up monitoring sensor.