• 한국CDE학회논문집
• /
• 제14권5호
• /
• pp.323-329
• /
• 2009

Auto-makers can only remain competitive by producing high quality vehicles in an efficient way. In designing a production line, one of the most important objectives of digital manufacturing is to verify design errors as early as possible. In terms of the cost and time saving, it is very essential to start the construction of a production line with a proven design which is error-free. Likewise, this paper aims to implement PLC verification using an example. The verification in automobile manufacturing means verifying PLC program, which control automatic devices. In this paper, we built a virtual factory to implement PLC simulation and introduced verification procedure using PLC Studio. Finally, we can prove the availability for the PLC verification.

• 제어로봇시스템학회논문지
• /
• 제2권1호
• /
• pp.53-59
• /
• 1996

An automatic verification method has been studied to determine the safety and operability of programmable logic controller (PLC) based systems. For the systematic and efficient verification, we have developed a conversion method from relay ladder logic (RLL) to the verification system description. RLL is a common representation used to document PLC programs for the sequential logic of the system such as the safety interlocks and the startup/shutdown procedures. Once the modules are developed, complex RLLs can be represented by the combination of modules. As a result we can verify complex PLC systems using the verification method including RLL modules. The developed modules are used to verify alarm systems and show that the method is valid.

• 대한안전경영과학회지
• /
• 제17권1호
• /
• pp.179-192
• /
• 2015

In an automated industry PLC plays a central role to control the automation system. Therefore, fault free operation of PLC controlled automation system is essential in order to maximize a firm's productivity. A prior test of control system is a practical way to check fault operations, but it is a time consuming job and can not check all possible fault operation. A formal verification of PLC program could be a best way to check all possible fault situation. Tracing the history of the study on formal verification, we found three problems, the first is that a formal representation of PLC control system is incomplete, the second is a state explosion problem and the third is that the verification result is difficult to use for the correction of control program. In this paper, we propose a transformation method to reproduce the control system correctly in formal model and efficient procedure to verify and correct the control program using verification result. To demonstrate the proposed method, we provided a suitable case study of an automation system.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2009년도 춘계학술대회 논문집
• /
• pp.25-26
• /
• 2009

• 한국CDE학회논문집
• /
• 제14권4호
• /
• pp.225-233
• /
• 2009

The objective of this paper is to examine a construction method and verify PLC logic using the logical modeling and simulation of a virtual plant has complex manufacturing system and the domain of application is car body assembly line of automotive industrial operated by PLC Program. The proposed virtual plant model for the analysis of the construction method consists of three types of components which are virtual device, intermediary transfer and controller is modeled by logical model but it the case of the verification of PLC program, HMI and PLC logic in the field substitute for the controller. The implementation of the proposed virtual plant model is conducted PLC Studio which is an object-oriented modeling language based on logical model. As a result, proposed methods enable 3D graphics is designed in the analysis step to use for verification of PLC program without special efforts.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
• /
• pp.2489-2491
• /
• 2005

Currently, Programmable Logic Contorller(PLC) uses Real Time Operation System(RTOS) as basic OS. RTOS executes defined results as to defined time. General features of RTOS emphasize the priority in each task, high-speed process of external interrupt, task scheduling, synchronization in task, the limitation of memory capacity. For safety critical placement, PLC software needs Verification and Validation(V&V). For example, nuclear power plant. In this paper, PLC RTOS is verified by formal methods. Particularly, formal method V&V uses verification tool called 'STATEMATE', and shows the results.

• Nuclear Engineering and Technology
• /
• 제41권1호
• /
• pp.79-90
• /
• 2009

Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
• /
• 제15권3호
• /
• pp.211-215
• /
• 2009

프로그래머블 로직 콘트롤러(PLC)가 원자력 계측제어 시스템과 같은 안전 필수 시스템 구현에 많이 사용됨에 따라, PLC 프로그램에 대한 정형검증의 필요가 높아지고 있다. 본 연구에서는 함수 블록 다이어램(FBD)으로 구현된 PLC 프로그램에 대한 자동화된 정형검증 기법을 제안한다. FBD 프로그램을 검증하기 위해서 먼저 FBD 프로그램을 검증언어인 Verilog로 변환하고, 변환된 Verilog모델에 대해 SMV 모델체커를 호출해 모델체킹을 수행한다. 자동화를 위해 FBD Verifier 도구를 개발하였다. FBD Verifier는 FBD 프로그램으로부터 Verilog 모델로의 자동변환 기능뿐 아니라 모델체킹 결과 생성된 반례를 직관적이고 효과적으로 분석할 수 있는 기능 또한 제공한다. 제안된 기법과 도구를 사용해 원전계측제어시스템 개발사업단의 원자로 보호시스템에 대한 방대한 양의 FBD 프로그램을 성공적으로 검증하였다.

• 한국CDE학회논문집
• /
• 제14권1호
• /
• pp.50-59
• /
• 2009

There are two main problems in the current PLC ladder programming practices: First, currently there are no widely adopted systematic design methods to deal with PLC based control systems in the shop floor. So, the control logic design phase is usually omitted in current PLC programming development life cycle. Second, PLC ladder logic provides only microscopic view of system processes. As a result, it is difficult for FA engineers to have overall perspectives about the interaction of system components intuitively during the verification step of logic errors. To solve these problems, this paper proposed object-oriented design and automatic generation method of PLC ladder logic. Based on the proposed method, the computer software to assist the automatic ladder logic generation is also developed.

• 한국정보과학회논문지:소프트웨어및응용
• /
• 제37권1호
• /
• pp.54-59
• /
• 2010

산업자동화 분야에는 특수목적 마이크로콘트롤러인 PLC가 널리 사용된다. PLC 프로그램 분석과 검증을 위한 연구에서 우선적으로 해야 할 일은 PLC 프로그래밍 언어의 의미구조를 정형적으로 제시하는 것이다. 본 논문은 PLC 프로그래밍에 널리 사용하는 LD 언어의 의미구조를 정의한다. LD 언어는 그래픽 언어이기 때문에 먼저 텍스트 언어 Symbolic LD로 구문구조를 정형화한 다음에, Symbolic LD에 대한 의미구조를 정의할 수가 있다. 본 논문은 Symbolic LD의 의미구조를 자연 의미구조 기법으로 정의하고, 증명 보조기 Coq을 이용하여 정형화하였다.