• Title/Summary/Keyword: Verification of PLC

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Design of a Vehicle Assembly Line Using PLC Simulation (PLC 시뮬레이션을 이용한 자동차 조립 라인 설계)

  • Lee, Chang-Ho;Wang, Gi-Nam;Park, Sang-Chul
    • Korean Journal of Computational Design and Engineering
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    • v.14 no.5
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    • pp.323-329
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    • 2009
  • Auto-makers can only remain competitive by producing high quality vehicles in an efficient way. In designing a production line, one of the most important objectives of digital manufacturing is to verify design errors as early as possible. In terms of the cost and time saving, it is very essential to start the construction of a production line with a proven design which is error-free. Likewise, this paper aims to implement PLC verification using an example. The verification in automobile manufacturing means verifying PLC program, which control automatic devices. In this paper, we built a virtual factory to implement PLC simulation and introduced verification procedure using PLC Studio. Finally, we can prove the availability for the PLC verification.

Development of PLC modules for the safety verification of chemical processes (공정의 안전 검증을 위한 PLC 모듈 개발)

  • Jeong, Sang-Hun;Lee, Kwang-Soon;Moon, Il
    • Journal of Institute of Control, Robotics and Systems
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    • v.2 no.1
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    • pp.53-59
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    • 1996
  • An automatic verification method has been studied to determine the safety and operability of programmable logic controller (PLC) based systems. For the systematic and efficient verification, we have developed a conversion method from relay ladder logic (RLL) to the verification system description. RLL is a common representation used to document PLC programs for the sequential logic of the system such as the safety interlocks and the startup/shutdown procedures. Once the modules are developed, complex RLLs can be represented by the combination of modules. As a result we can verify complex PLC systems using the verification method including RLL modules. The developed modules are used to verify alarm systems and show that the method is valid.

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Formal Verification of PLC Program Safety in Manufacturing Automation System (생산자동화시스템 PLC 제어프로그램의 안전성 정형검증에 관한 연구)

  • Park, Chang Mok
    • Journal of the Korea Safety Management & Science
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    • v.17 no.1
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    • pp.179-192
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    • 2015
  • In an automated industry PLC plays a central role to control the automation system. Therefore, fault free operation of PLC controlled automation system is essential in order to maximize a firm's productivity. A prior test of control system is a practical way to check fault operations, but it is a time consuming job and can not check all possible fault operation. A formal verification of PLC program could be a best way to check all possible fault situation. Tracing the history of the study on formal verification, we found three problems, the first is that a formal representation of PLC control system is incomplete, the second is a state explosion problem and the third is that the verification result is difficult to use for the correction of control program. In this paper, we propose a transformation method to reproduce the control system correctly in formal model and efficient procedure to verify and correct the control program using verification result. To demonstrate the proposed method, we provided a suitable case study of an automation system.

A Study and Application of Methodology for Applying Simulation to Car Body Assembly Line using Logical Model (Logical 모델을 활용한 자동차 차체 조립 라인의 시뮬레이션 적용을 위한 방안 연구 및 적용)

  • Koo, Lock-Jo;Park, Snag-Chul;Wang, Gi-Nam
    • Korean Journal of Computational Design and Engineering
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    • v.14 no.4
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    • pp.225-233
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    • 2009
  • The objective of this paper is to examine a construction method and verify PLC logic using the logical modeling and simulation of a virtual plant has complex manufacturing system and the domain of application is car body assembly line of automotive industrial operated by PLC Program. The proposed virtual plant model for the analysis of the construction method consists of three types of components which are virtual device, intermediary transfer and controller is modeled by logical model but it the case of the verification of PLC program, HMI and PLC logic in the field substitute for the controller. The implementation of the proposed virtual plant model is conducted PLC Studio which is an object-oriented modeling language based on logical model. As a result, proposed methods enable 3D graphics is designed in the analysis step to use for verification of PLC program without special efforts.

PLC Real Time OS Verification & Validation in Formal Methods (정형기법을 이용한 PLC RTOS 검증)

  • Choi, Chang-Ho;Song, Seung-Hwan;Yun, Dong-Hwa;Hwang, Sung-Jae
    • Proceedings of the KIEE Conference
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    • 2005.07d
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    • pp.2489-2491
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    • 2005
  • Currently, Programmable Logic Contorller(PLC) uses Real Time Operation System(RTOS) as basic OS. RTOS executes defined results as to defined time. General features of RTOS emphasize the priority in each task, high-speed process of external interrupt, task scheduling, synchronization in task, the limitation of memory capacity. For safety critical placement, PLC software needs Verification and Validation(V&V). For example, nuclear power plant. In this paper, PLC RTOS is verified by formal methods. Particularly, formal method V&V uses verification tool called 'STATEMATE', and shows the results.

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VERIFICATION OF PLC PROGRAMS WRITTEN IN FBD WITH VIS

  • Yoo, Jun-Beom;Cha, Sung-Deok;Jee, Eun-Kyung
    • Nuclear Engineering and Technology
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    • v.41 no.1
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    • pp.79-90
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    • 2009
  • Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design.

A Formal Verification Technique for PLC Programs Implemented with Function Block Diagrams (함수 블록 다이어그램으로 구현된 PLC 프로그램에 대한 정형 검증 기법)

  • Jee, Eun-Kyoung;Jeon, Seung-Jae;Cha, Sung-Deok
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.3
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    • pp.211-215
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    • 2009
  • As Programmable Logic Controllers (PLCs) are increasingly used to implement safety critical systems such as nuclear instrumentation & control system, formal verification for PLC based programs is becoming essential. This paper proposes a formal verification technique for PLC program implemented with function block diagram (FBD). In order to verify an FBD program, we translate an FBD program into a Verilog model and perform model checking using SMV model checker We developed a tool, FBD Verifier, which translates FBD programs into Verilog models automatically and supports efficient and intuitive visual analysis of a counterexample. With the proposed approach and the tool, we verified large FBD programs implementing reactor protection system of Korea Nuclear Instrumentation and Control System R&D Center (KNICS) successfully.

UML-based PLC Ladder Logic Design and Automatic Generation of Ladder Code (UML 기반 PLC 래더 로직 설계와 코드 자동 생성)

  • Han, Kwan-Hee;Park, Jun-Woo
    • Korean Journal of Computational Design and Engineering
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    • v.14 no.1
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    • pp.50-59
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    • 2009
  • There are two main problems in the current PLC ladder programming practices: First, currently there are no widely adopted systematic design methods to deal with PLC based control systems in the shop floor. So, the control logic design phase is usually omitted in current PLC programming development life cycle. Second, PLC ladder logic provides only microscopic view of system processes. As a result, it is difficult for FA engineers to have overall perspectives about the interaction of system components intuitively during the verification step of logic errors. To solve these problems, this paper proposed object-oriented design and automatic generation method of PLC ladder logic. Based on the proposed method, the computer software to assist the automatic ladder logic generation is also developed.

Formalization of Ladder Diagram Semantics Using Coq (증명보조기 Coq을 이용한 래더 다이어그램 의미구조의 정형화)

  • Shin, Seung-Cheol
    • Journal of KIISE:Software and Applications
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    • v.37 no.1
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    • pp.54-59
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    • 2010
  • Special-purpose microcontrollers PLCs have been widely used in the area of industrial automation. For the research of analysis and verification for PLC programs, first of all we have to specify formal sematics of PLC programming languages. This paper defines formally the operational semantics of LD language. After we transform the graphical language LD into its textual representation Symbolic LD, we give semantics of Symbolic LD since LD language is a graphical language. This paper defines the natural sematics of Symbolic LD and formalizes it in Coq proof assistant.