• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.68-73
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• 2006

This, paper proposes a cosimulation methodology that results in an efficient SoC design as well as fast verification by integrating HDL, SystemC, and algorithm-level abstraction using the design tools Active-HDL and Matlab's Simulink. To demonstrate the proposed design methodology, we implemented the design technique on a serial connection multi-channel speaker system. We have demonstrated the proposed cosimulation method utilizing an ARM processor based SoC Master board with the AMBA bus interface and a Xilinx Vertex4 FPGA. The proposed method has the advantage of simultaneous simulation verification of both software and hardware parts in high levels of abstraction mixed with some performance critical parts in more concrete RTL codes. This allows relatively fast and easy design of a speaker connection system which typically requires significant amount of data processing for verification.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.68-73
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• 2008

In this paper, we propose watermark algorithm called TDWA(Time-Division Watermarking Algorithm) and we applied the proposed algorithm to H.264 video coding standard. We establish that a proposed algorithm is applied to H.264 baseline profile CODEC. The proposed algorithm inserts a watermark into the spatial domain of several frames. We can easily insert strong and invisible watermarks into original pictures using this method. For verification of the proposed algorithm we design hardware core using Verilog-HDL and Excalibur for JM 8.7 code with hardware & software co-simulation. As a result of verification, the PSNR between watermarked pictures and original pictures are more than 60dB and we found the watermark is kept more than 80% after encoding of H.264/AVC with quantization parameter of 28 in baseline profile.

• Aerospace Engineering and Technology
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• v.12 no.2
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• pp.14-23
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• 2013

Fault management design of the satellite describes preparations for failures which can occur during operational phase. Fault management design contains detection and isolation function of anomaly, and also it contains function to maintain the satellite in safe condition until the ground station finds out a cause of failure and takes a countermeasure. Unlike normal operation, safing operation is automatically performed by Power Control and Distribution Unit and Integrated Bus Management Unit which loads Flight Software without intervention of ground station. Since fault management operation is automatical, fault management logic and functionality of relevant hardware should be thoroughly checked during ground test phase, and error which is similar to actual should be carefully applied without damage. Verification test for fault management design is conducted for various subsystems of satellite. In this paper, we show the design process of fault management design verification test for Electrical Power Subsystem and Attitude and Orbit Control Subsystem of Low Earth Orbit satellite flight model and the test results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.525-532
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• 2013

Recently. smartphones have been popularized rapidly and now located deep in our daily life, providing a variety of services from banking, SNS (Social Network Service), and entertainment to smart-work mobile office through apps. Such smartphone apps can be easily downloaded from what is known as app store which, however, bears many security issues as software developers can just as easily upload to it. Military apps will be exposed to a myriad of security threats if distributed through internet-basis commercial app store. In order to mitigate such security concerns, this paper suggests a security guidelines for establishing a military-excusive app store and security verification system which prevent the security hazards that can occur during the process of development and distribution of military-use mobile apps.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.124-129
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• 2013

This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.

• The KIPS Transactions:PartD
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• v.15D no.1
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• pp.99-106
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• 2008

Recently developed compilers perform some optimizations in order to speed up the execution time of source program. These optimizations require the reordering of the sequence of program statements. This reordering does not give any problems in a single-threaded program. However, the reordering gives some significant errors in a multi-threaded program. State-of-the-art model checkers such as JavaPathfinder do not consider the reordering resulted in the optimization step in a compiler since they just consider a single memory model. In this paper, we develop a new verification tool to verify Java source program based on Java Memory Model. And our tool is capable of handling the reordering in verifying Java programs. As a result, our tool finds an error in the test program which is not revealed with the traditional model checker JavaPathFinder.

• Journal of IKEEE
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• v.22 no.4
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• pp.1073-1078
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• 2018

As interest in the 4th Industrial Revolution increases, the CPS, in which things existing in the reality and things existing in the virtual interact with each other, is attracting attention as an important technology. Complex systems such as electric vehicles, autonomous driving, smart factories, and smart grid system are considered as core technology fields of the 4th Industrial Revolution, and many types of research have been conducted to develop it. The reliability of the system is directly related to the safety of people in case of the autonomous driving, and verification of the actual vehicle's hardware and software of ADAS is essential. In this paper, we proposed distributed simulation middleware supporting HILS for reliable verification of the complex hybrid systems.

• Journal of the Korean Society of Marine Environment & Safety
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• v.25 no.3
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• pp.269-277
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• 2019

Since 2020, according to the International Convention for the Prevention of Pollution from Ships (MARPOL) amended in 2016, each Administration shall transfer the annual fuel consumption of its registered ships of 5,000 gross tonnage and above to the International Maritime Organization (IMO) after verifying them. The Administration needs stacks of materials, which must not be manipulated by ship companies, including the Engine log book and also bears an administrative burden to verify them by May every year. This study considers using the Automatic Identification System (AIS), mandatory navigational equipment, as an objective and efficient tool among several verification methods. Calculating fuel consumption using a ship's speed in AIS information based on the theory of a relationship between ship speed and fuel consumption was reported in several examples of relevant literature. After pre-filtering by excluding AIS records which had speed errors from the raw data of five domestic cargo vessels, fuel consumptions calculated using Excel software were compared to actual bunker consumptions presented by ship companies. The former consumptions ranged from 96 to 123 percent of the actual bunker consumptions. The difference between two consumptions could be narrowed to within 20 percent if the fuel consumptions for boilers were deducted from the actual bunker consumption. Although further study should be carried out for more accurate calculation methods depending on the burning efficiency of the engine, the propulsion efficiency of the ship, displacement and sea conditions, this method of calculating annual fuel consumption according to the difference between two consumptions is considered to be one of the most useful tools to verify bunker consumption.

• Journal of the Korea Society for Simulation
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• v.19 no.4
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• pp.161-167
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• 2010

To realize the U-healthcare system, the mobile patient monitoring system is of the essence. In this monitoring system, a patient's real-time data on biometrics and location must be transferred to predeterminate destination server ceaselessly. As the number of mobile patients increases steadily or mobile patients are moving into some specific area, the load balancing solution to real-time data congestion problem is needed. In this paper, we propose a new mobile patient monitoring system with Torus topology where three layers are connected hierarchically and the intermediate layer takes charge of priority-based load balancing. For the formalized design and verification of proposed system, we describe the overall structure with connectivity among its components and implement major components in pseudo-code by adopting a system specification-based approach. This approach makes the design and verification of our mobile patient monitoring system more flexible and accurate.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.11
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• pp.4460-4467
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• 2010

Recent advances in computer technology have brought more dependence on software to railway systems and changed to computer systems. Hence, the reliability and safety assurance of the vital software running on the embedded railway system is going to tend toward very critical task. Accordingly, various software test and validation activities are highly recommended in the international standards related railway software. In this paper, we presented an automated analysis tool and standard for software testing coverage in railway system, and presented its result of implementation. We developed the control flow analysis tool estimating test coverage as an important quantitative item for software safety verification in railway software. Also, we proposed judgement standards due to railway S/W Safety Integrity Level(SWSIL) based on analysis of standards in any other field for utilizing developed tool widely at real railway industrial sites. This tool has more advantage of effective measuring various test coverages than other countries, so we can expect railway S/W development and testing technology of real railway industrial sites in Korea.