• Journal of Service Research and Studies
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• v.8 no.1
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• pp.59-72
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• 2018

In the perspective of service, it is important to institute certification process required by International Standard Organization (ISO) for software (SW) development process, since Information and Communication Technology (ICT) takes high portion of the Korean industry and its certification for SW is essential internationally for trade. In addition, the certification service provided by BPMN tools like ADONIS is absolutely necessary. In that perspective, this paper proposes a new approach to satisfy this kind of necessity. This approach provides the certification service for the safety of SW required at the international level in Korean industry. Furthermore, the approach can be applied to other domains beside the SW. In order to demonstrate the approach, this paper shows how to guarantee service design for certification of ECSS-E-40 of European Space Agency (ESA) with ADONIS. This paper focuses on specification and verification of SW in E-40, and the main requirement for the verification will be safety of the SW.

• Journal of the Korea Society for Simulation
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• v.27 no.3
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• pp.23-36
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• 2018

Discrete Event System Specification (DEVS) has been used for decades as it provides sound semantics for hierarchical modular specification of discrete event systems. Instead of the mathematical specification, the DEVS diagram, based on the structured DEVS formalism, has provided more intuitive and convenient representation of complex DEVS models. This paper proposes a clean room process for implementation and verification of a DEVS diagram model specification into a simulation software source code. Specifically, it underlies a sequence of transformation steps from conformance and integrity checking of a given diagram model, translation into a corresponding tabular model, and finally conversion to a simulation source code, with each step being inversely verifiable for traceability. A simple example helps developers to understand the proposed process with associated transformation methods; a case study shows that the proposed process is effective for and adaptable to practical simulation software development.

• Journal of Software Assessment and Valuation
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• v.16 no.1
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• pp.37-44
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• 2020

The similarity of the software is extracted by the verification of comparing with the source code. The source code is the intellectual copyright of the developer written in the programming language. And the source code written in text format contains the contents of the developer's expertise and ideas. The verification for judging the illegal use of software copyright is performed by comparing the structure and contents of files with the source code of the original and the illegal copy. However, there is hard to do the one-to-one comparison in practice. Cause the suspected source code do not submitted Intentionally or unconsciously. It is now increasing practically. In this case, the comparative evaluation with execution code should be performed, and indirect methods such as reverse assembling method, reverse engineering technique, and sequence analysis of function execution are applied. In this paper, we analyzed the effectiveness of indirect comparison results by practical evaluation . It also proposes a method to utilize to the system and executable code files as a verification results.

• Journal of KIISE:Computing Practices and Letters
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• v.12 no.2
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• pp.141-148
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• 2006

This paper suggests method of safe security S/W by verifying and its result of formal verification tool. We will survey many formal verification tools and compare features of these tools. And we will suggest what tool is appropriate and methodogoly of developing safe security S/W. The Z/EVES is the most appropriate tool. This paper proposes formal verification of ACS by using RoZ tool which is formal verification tool to create UML model. The specification and verification are executed using Z/EVES tool. These procedures can find weak or wrong point of developed S/W.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.706-710
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• 2003

In this paper, we will present brief design feature, implementations, and tests for verification of KOMPSAT-2 simulator, which is a subsystem of KOMPSAT-2 MCE. SIM is implemented on PC server to minimize costs and troubles on embedding onboard flight software into SIM, OOA/OOD methodology is employed to maximized S/W reusability, and XML is used for S/C characteristics, TC, TM and Simulation data instead of commercial DB. Consequently, we can reduce costs for the system, efforts embedding flight software, and maximize software reusability. SIM subsystem test was performed successfully.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.65 no.4
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• pp.242-249
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• 2016

The railway system is being converted to the computer system from the existing mechanical device, and the dependency on software is being increased rapidly. Though the size and degree of complexity of software for railway system are slower than the development speed of hardware, it is expected that the size will be grown bigger gradually and the degree of complexity will be increased also. Accordingly, the validation of reliability and safety of embedded software for railway system was started to become influential as the important issue. Accordingly, various software test and validation activities are highly recommended in the international standards related railway software. In this paper, we presented a software coding analysis tool using symbolic execution for railway system, and presented its result of implementation.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.1
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• pp.30-35
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• 2013

Many function of railway signalling system which is in charge of most core function in a railway system are being operated by the software according to the development of computer technology. Accordingly, the source code testing to verify the safety of the railway signalling system software becomes to be more important, and related international standards highly recommend verifications on the source code also. For this reason, several related studies on vital source code verification were executed from several years ago in Korea. This paper performed tests through the application to railway signalling system being applied to the existing actual domestic railway sites through automated testing tools for coding rules of signalling system software and another signaling system software under development in Korea recently, and analyzed their results.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.261-267
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• 2002

In SOC(System On a Chip) designs, reducing time and cast for design verification is the most critical to improve the design productivity. this is mainly because the designs require co-verifying HW together with SW, which results in the increase of verification complexity drastically. In this paper, to cope with the verification crisis in SOC designs, we propose a new verification methodology, so called integrated co-verification, which lightly combine both co-simulation and co-emulation in unified and seamless way. We have applied our integrated co-verification to ARM/AMBA platform-based co-verification environment with a commercial co-verification tool, Seamless CVE, and a physical prototyping board. The experiments has shown clear advantage of the proposed technique over conventional ones.

• ETRI Journal
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• v.33 no.3
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• pp.423-433
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• 2011

This paper introduces an adaptive and integrated utterance verification (UV) framework using minimum verification error (MVE) training as a new set of solutions suitable for real applications. UV is traditionally considered an add-on procedure to automatic speech recognition (ASR) and thus treated separately from the ASR system model design. This traditional two-stage approach often fails to cope with a wide range of variations, such as a new speaker or a new environment which is not matched with the original speaker population or the original acoustic environment that the ASR system is trained on. In this paper, we propose an integrated solution to enhance the overall UV system performance in such real applications. The integration is accomplished by adapting and merging the target model for UV with the acoustic model for ASR based on the common MVE principle at each iteration in the recognition stage. The proposed iterative procedure for UV model adaptation also involves revision of the data segmentation and the decoded hypotheses. Under this new framework, remarkable enhancement in not only recognition performance, but also verification performance has been obtained.

• Journal of the Institute of Convergence Signal Processing
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• v.13 no.4
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• pp.211-219
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• 2012

In this paper, we described the software development for verifying the integrity of output data of TCP/IP for VLBI Correlation Subsystem (VCS) correlation block and proposed the performance improvement method in order to prevent the data loss of correlation output. The VCS correlation results are saved at the Data Archive system through TCP/IP packet transmission. In this paper, the integrity verification software is developed so as to confirm the integrity of correlation result saved at the data archive system using TCP/IP packet information of VCS. The 3-step integrity verification process is proposed by using the developed software, its effectiveness was confirmed in consequence of correlation experiments. In addition, TCP/IP packet transmission must be completed within minimum integration period. However, there is not only TCP/IP packet loss occurred but also the problem of correlation result integrity affected in account of a large quantity of packets and data during short integration time. In this paper, the reason of TCP/IP packet loss is analyzed and the modified methods for FPGA(Field Programmable Gate Array) of VCS are proposed, the integrity problem of correlation results will be solved.