• Transactions of Materials Processing
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• v.7 no.5
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• pp.450-458
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• 1998

The high temperature deformation behavior of Al 5083 alloy has been studied in the temperature range of 350 to 520 ${\circ}C$ and strain rate range of 0.2 to 3.0/sec by torsion test. The strain rate sensitivity(m) of the material was evaluated and used for estabilishing power dissipation maps following the dynamic material model. These maps show the variation of efficiency of power dissipation(${\eta}$=2m/(2m+1)) with temperature and strain rate. Hot restoration of dynamic recrystallization (DRX) was analyzed from the flow curve, deformed microstructure, and processing maps during hot deformation. Also, the effect of deformation strain on the efficiency of power dissipation of the alloy was analysed using the processing maps. Moreover relationship between the hot-ductility and efficiency of power dissipation of the alloy depending on thmperature and strain rate was studied using the Zener-Hollomon parameter(Z=${\varepsilon}$exp(Q/RT) It is found that the maximum efficiency of power dissipation for DRX in Al 5083 alloy is about 74.6 pct at the strain of 0.2. The strain rate and temperature at which the efficiency peak occurred in the DRX domain is found to be ∼0.1/sec and ∼450${\circ}C$ respectively.

• Journal of Digital Contents Society
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• v.9 no.3
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• pp.471-481
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• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

• The Magazine of the Society of Air-Conditioning and Refrigerating Engineers of Korea
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• v.17 no.2
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• pp.131-139
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• 1988

The thermoacoustic oscillation induced in an air column with variable cross section area is investigated theoretically and experimentally. The onset condition of the oscillation is derived by equating the acoustic power production to the power dissipation. The power production at the heater is predicted by using the efficiency factor obtained by heat transfer analysis for a single wire in a uniform cross flow and considering the interference between heater wires. The power dissipation is estimated by measuring the attenuating coefficient from the pressure decay curve. The theoretical prediction to the onset condition of the oscillation is confirmed experimentally. The effect of the variation of the column cross section area on the onset condition is presented.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.712-719
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• 2012

This paper presents Single-bit Third order Delta-Sigma Modulator, which can be applied to the Low speed High resolution ADC in Audio signal Process System. Whereas the Operational Amplifier in modulator consumed static power dissipation in operating, this modulator used Switching on/off techniques, which makes the Power dissipation of the modulator reduced. Also proposed modulator minimizes frequency characteristic variation by optimizing switch position. And this modulator chooses Single-bit type to guarantee stability. The designed ADC went through 0.35um CMOS n-well 1-poly 4-metal process to be a final product, and the final product has shown 17.1mW of power dissipation with 3.3V of Supply Voltage, 6.4MHz of conversion rate. And 84.3dB SNDR and 13.5bit ENOB with 20KHz of input frequency.

• 한국신재생에너지학회:학술대회논문집
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• 2005.06a
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• pp.516-519
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• 2005

The pilot tidal current power plant is to be constructed at the Uldolmok between Chindo and Haenam, during next year. and extensive coastal engineering research works have been carried out. In this paper we describes some observation results of the tide and tidal current. as well as modeling work in order to investigate the tide and tidal current regime change in relation to the tidal current power plant (TCPP) construction. The special modeling skill in order to consider the turbine operation in the TCPP is developed and applied to the estimation for the flow regime change by the simple layout of the tidal current power plant.

• New & Renewable Energy
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• v.1 no.2 s.2
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• pp.73-78
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• 2005

The pilot tidal current power plant is to be constructed at the Uldolmok between Chindo and Haenam, during next year, and extensive coastal engineering research works have been carried out. In this paper we describes some observation results of the tide and tidal current, as well as modeling work in order to investigate the tide and tidal current regime change In relation to the tidal current power plant [TCPP] construction. The special modeling skill in order to consider the turbine operation in the TCPP is developed and applied to the estimation for the flow regime change by the simple layout of the tidal current power plant.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2110-2113
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• 1999

This paper describes the initial characteristics of turbine generators at the Taean thermal power plant #4 and Wolsong nuclear power plant #2. The turbine generators had been in service for two years. The insulation diagnostic tests included measurements of insulation resistance, polarization index, ac current, dissipation factor($tan{\delta}$) and partial discharges (PD). The values of ac current and tan a were measured by Schering bridge. PD measurements were conducted using digital PD detector. The variation of $tan{\delta}$ and PD was confirmed in two generator stator insulations.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.707-710
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• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.397-404
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• 2012

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.