• Title/Summary/Keyword: VLST test

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Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development

  • Sato, Masayuki;Wakamatsu, Hiroki;Arai, Masayuki;Ichino, Kenichi;Iwasaki, Kazuhiko;Asakawa, Takeshi
    • Journal of Information Processing Systems
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    • v.4 no.4
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    • pp.121-132
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    • 2008
  • VLSI chips have been tested using various automatic test equipment (ATE). Although each ATE has a similar structure, the language for ATE is proprietary and it is not easy to convert a test program for use among different ATE vendors. To address this difficulty we propose a tester structure expression language, a tester language with a novel format. The developed language is called the general tester language (GTL). Developing an interpreter for each tester, the GTL program can be directly applied to the ATE without conversion. It is also possible to select a cost-effective ATE from the test program, because the program expresses the required ATE resources, such as pin counts, measurement accuracy, and memory capacity. We describe the prototype environment for the GTL and the tester selection tool. The software size of the prototype is approximately 27,800 steps and 15 manmonths were required. Using the tester selection tool, the number of man-hours required in order to select an ATE could be reduced to 1/10. A GTL program was successfully executed on actual ATE.

Design and Verification of a CAN Protocol Controller for VLSI Implementation (VLSI 구현을 위한 CAN 프로토콜 컨트롤러의 설계 및 검증)

  • Kim, Nam-Sub;Cho, Won-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.2 s.344
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    • pp.96-104
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    • 2006
  • This paper presents design methodology, encient verification and implementation of a CAN protocol controller. The design methodology uses a heuristic technique to make the design flexible and cost effective. Using the design methodology, we created architecture for a CAN controller which has flexible and low cost features. For faster time-to-market and reliable operation of the designed CAN protocol controller, we p개posed a three-step verification process which uses three different kinds of verification techniques. The goal of this three-step verification is to reduce the number of test sequences in order to rapidly implement the design without loss of reliability for faster time-to-market. The designed CAN protocol controller was fabricated using a 0.35 micrometer CMOS technology.