Journal of Information Processing Systems

Korea Information Processing Society (한국정보처리학회)
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Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development

  • Published : 2008.12.31
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Abstract

VLSI chips have been tested using various automatic test equipment (ATE). Although each ATE has a similar structure, the language for ATE is proprietary and it is not easy to convert a test program for use among different ATE vendors. To address this difficulty we propose a tester structure expression language, a tester language with a novel format. The developed language is called the general tester language (GTL). Developing an interpreter for each tester, the GTL program can be directly applied to the ATE without conversion. It is also possible to select a cost-effective ATE from the test program, because the program expresses the required ATE resources, such as pin counts, measurement accuracy, and memory capacity. We describe the prototype environment for the GTL and the tester selection tool. The software size of the prototype is approximately 27,800 steps and 15 manmonths were required. Using the tester selection tool, the number of man-hours required in order to select an ATE could be reduced to 1/10. A GTL program was successfully executed on actual ATE.

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References

  1. Semiconductor Industry Association, International Technology Roadmap for Semiconductors. 2007. http://www.itrs.net/
  2. T. Kazamaki, H. Maruyama, and S. Sumida, “Trial Model of 100 MHz Test Station for High Speed LSI Test System,” International Test Conference, pp. 611-617, 1978
  3. T. Kazamaki, “A 100MHz Tester - Challenge to New Horizon of Testing High Speed LSI,” International Test Conference, pp. 618-625, 1979
  4. S. Bisset, “The Development of a Tester-per-Pin VLSI Test System Architecture,” International Test Conference, pp. 151-157, 1983
  5. J. Katz and R. Rajsuman, “A New Paradigm in Test for the Next Millennium,” International Test Conference, pp. 468-476, 2000 https://doi.org/10.1109/TEST.2000.894239
  6. J. Bedsole, R. Raina, A. Crouch, and M. S. Abadir, “Very Low Cost Testers: Opportunities and Challenges,” IEEE Design & Test of Computers, Vol.18, No.5, pp. 60-69, Sep.-Oct. 2001 https://doi.org/10.1109/54.953273
  7. K. Posse and G. Eide, “Key Impediments to DFTFocused Test and How to Overcome Them,” International Test Conference, pp. 503-511, 2003
  8. M. Sato, N. Otsuka, O. Muto, M. Arai, S. Fukumoto, K. Iwasaki, K. Uehara, I. Shimizu, and H. Mamyouda, “Development of Low-Power Board-Mounted Reconfigurable Tester,” IEICE Transactions on Information and Systems, Vol. J88-D-I, No. 6, pp. 1065-1075, June 2005. (in Japanese)
  9. J386A/J386A-8 Customer Service Manual, Teradyne, April 1985
  10. 8311122, VLSI Test System (ATL-30) Programming Handbook, Advantest, 1998
  11. M. Sato, “Memory Virtual Tester Technology and a Tester on Chip,” SEMI Technology Symposium, pp. 70-75, December 2000
  12. IEEE Standard Test Interface Language (STIL) for Digital Test Vector, IEEE Std. 1450-1999
  13. Japan Electronics and Information Technology Industries Association, Semiconductor Technology Roadmap Committee of Japan, 2003
  14. M. Sato, H. Wakamatsu, and K. Iwasaki, “Investigation of a Tester Language and a Tester Structure Expression Language,” SEMI Technology Symposium, pp. 4.21-4.24, December 2000
  15. Test Systems Strategies, Inc., http://www.tssi.com/