• Journal of Korean Neurosurgical Society
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• v.56 no.4
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• pp.344-347
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• 2014

Stent thrombosis is a major limitation of stent-assisted coiling, which is an effective method for treating wide-necked aneurysms. Although early in-stent thrombosis has been reported, very late stent thrombosis (VLST) (>1 year) has not been reported following implantation of a single self-expandable stent designed for coiling. Herein, the authors present a case of VLST that occurred 14 months after single stent implantation in a large paraclinoid aneurysm with an ultra-wide neck involving the parent artery circumferentially. This case indicates the need for establishing guidelines regarding the optimal duration of prophylactic antiplatelet therapy following stent-assisted coiling, which remains undefined in the neuroendovascular field.

• The Journal of the Korea Contents Association
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• v.13 no.12
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• pp.880-892
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• 2013

Stent thrombosis after successful drug-eluting stent(DES) implantation has been reported in around 1% of patients in clinical trials. However, the increased risk of ST associated with DES remains a matter of concern. From 1 June 2003 to 30 June 2013, we investigated clinical characteristics, in-hospital outcomes in 10,273 patients who underwent percutaneous coronary intervention in the Heart Center of CNUH. Overall incidence of ST was 1.30% (134 patients). The incidence of ST according to the stent generations and the timing of ST (n=total, early vs. late vs. very late) were 0.79% (n=81, 26 vs. 12 vs. 43) in first-generation, 0.38% (n=39, 21 vs. 9 vs. 9) in second-generation and 0.14% (n=14, 8 vs 3 vs. 3) in third-generation, (p=0.70). The mortality from ST was significantly higher in early ST group compared to the late and very late ST groups (18.2% vs. 8.3% vs. 3.6%, p=0.042). Overall incidence of ST after DES implantation was 1.30% (134 patients). The in-hospital mortality was significantly higher in early ST group compared to the late and very late ST groups.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.96-104
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• 2006

This paper presents design methodology, encient verification and implementation of a CAN protocol controller. The design methodology uses a heuristic technique to make the design flexible and cost effective. Using the design methodology, we created architecture for a CAN controller which has flexible and low cost features. For faster time-to-market and reliable operation of the designed CAN protocol controller, we p개posed a three-step verification process which uses three different kinds of verification techniques. The goal of this three-step verification is to reduce the number of test sequences in order to rapidly implement the design without loss of reliability for faster time-to-market. The designed CAN protocol controller was fabricated using a 0.35 micrometer CMOS technology.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1329-1336
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• 1996

In many image compression applications, the discrete cosine transform (DCY) is well known for is highly efficient coding performance. However, it produces undesirable block artifacts in low-bit rate coding. In addition, in many practical applications, faster computation and easier VLST implementation of DCT coefficients are also important issues. The removal of the block artifacts and faster DCT computation are therefor of practical interest. In this paper, a modified DCTcomputation scheme was investigated, which provides a simple efficient solution to the reduction of the block artifacts while achieving faster computation. We have applied the new ap-proach to the low-bit rate coding and decoding of images. Simulation results on real images have verified the improved performance of the proposed method over the standar d method.

• Journal of Information Processing Systems
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• v.4 no.4
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• pp.121-132
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• 2008

VLSI chips have been tested using various automatic test equipment (ATE). Although each ATE has a similar structure, the language for ATE is proprietary and it is not easy to convert a test program for use among different ATE vendors. To address this difficulty we propose a tester structure expression language, a tester language with a novel format. The developed language is called the general tester language (GTL). Developing an interpreter for each tester, the GTL program can be directly applied to the ATE without conversion. It is also possible to select a cost-effective ATE from the test program, because the program expresses the required ATE resources, such as pin counts, measurement accuracy, and memory capacity. We describe the prototype environment for the GTL and the tester selection tool. The software size of the prototype is approximately 27,800 steps and 15 manmonths were required. Using the tester selection tool, the number of man-hours required in order to select an ATE could be reduced to 1/10. A GTL program was successfully executed on actual ATE.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1891-1894
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• 1999

We can classify the scratches after CMP process into micro-scratch and macro-scratches according to the scratch size, scratch intensity and defect map, etc. The micro-scratches on wafer after CMP process are discussed in this paper. From many causes, major factor that influences the formation of micro-scratch is known as particle size distribution of slurry.(1) It is indefinite what size or type of particle can cause micro-scratch on wafer surface, but there is possibility caused by large particle over 1um. The best way for controlling these large particle to inflow is to use the slurry filter on POU(Point of user). But the slurry filter(especially, depth-type filter) has sometimes the problem which makes more sever micro-scratches on wafer surface after CMP. We studied that depth-type slurry filter has what kind of week-points and the number of scratch could be reduced by lowering slurry flow rate and by using high spray bar which sprays DIW on polishing pad with high pressure.