• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.89-96
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• 2002

In this paper, the ADI(Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and the architecture designed through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using $0.6{\mu}m$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

• ETRI Journal
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• v.21 no.4
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• pp.1-8
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• 1999

Thick metal 0.8${\mu}m$ CMOS technology on high resistivity substrate(RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15mA that is an excellent noise performance compared with the offchip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integrating of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatibel process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.571-574
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• 2008

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.3
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• pp.60-67
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• 1985

A new glut bel routing technique for gate array is described in this paper. In former global routers the position of pins is considered to be in the center of the cell. So it is impossible to exactly estimate the number of signal lines passing through each channel. As a result, an overflow occurs and the overflow violates 100% wiring in detailed routing pro-cesses. Besides this, there are some problems in former global routers, for example, design time and cost, etc. This paper proposed a new algorithm in which pins ordering is considered to solve these problems. Using this algorithm, a global router is developed. Program experiments show the efficiency of the proposed algorithm.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2000-2003
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• 2002

In this paper, an IC chip of a cell- network type circuit constructed with 1-dimensional chaos circuits is reported. The circuit, is designed by sing switched-current (Sl) techniques. In the proposed circuit, by controlling connections of cells, an S- dimensional circuit (S ＝ 1, 2, 3,…) and a synchronization system can be constructed easily. Furthermore, in spite of faults of a few cells, the circuit can reconstruct above-mentioned systems only to change connections of cells. This feature will open up new vista for engineering applications which are used in a distance place such as space, deep sea, etc. since it is difficult to repair faults of these application systems. To investigate the characteristics of the circuit, SPICE simulations are performed. The VLSI chip is fabricated from the layout design using a CAD tool, MAGIC. The proposed circuit is integrable by a standard 1.2 $\mu\textrm{m}$ CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.3
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• pp.531-536
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• 2009

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.85-96
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• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.4
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• pp.1765-1794
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• 2019

Genetic Programming (GP) is an intelligence technique whereby computer programs are encoded as a set of genes which are evolved utilizing a Genetic Algorithm (GA). In other words, the GP employs novel optimization techniques to modify computer programs; imitating the way humans develop programs by progressively re-writing them for solving problems automatically. Trial programs are frequently altered in the search for obtaining superior solutions due to the base is GA. These are evolutionary search techniques inspired by biological evolution such as mutation, reproduction, natural selection, recombination, and survival of the fittest. The power of GAs is being represented by an advancing range of applications; vector processing, quantum computing, VLSI circuit layout, and so on. But one of the most significant uses of GAs is the automatic generation of programs. Technically, the GP solves problems automatically without having to tell the computer specifically how to process it. To meet this requirement, the GP utilizes GAs to a "population" of trial programs, traditionally encoded in memory as tree-structures. Trial programs are estimated using a "fitness function" and the suited solutions picked for re-evaluation and modification such that this sequence is replicated until a "correct" program is generated. GP has represented its power by modifying a simple program for categorizing news stories, executing optical character recognition, medical signal filters, and for target identification, etc. This paper reviews existing literature regarding the GPs and their applications in different scientific fields and aims to provide an easy understanding of various types of GPs for beginners.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.105-111
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• 2024

This paper deals with the minimum linear arrangement(MinLA) of a lattice graph, to which an approximate algorithm of linear complexity O(n) remains as a viable solution, deriving the optimal MinLA of 31,680 for 33×33 lattice. This paper proposes a partitioning arrangement algorithm of complexity O(1) that delivers exact solution to the minimum linear arrangement. The proposed partitioning arrangement algorithm could be seen as loading boxes into a container. It firstly partitions m rows into r₁,r₂,r₃ and n columns into c₁,c₂,c₃, only to obtain 7 containers. Containers are partitioning with a rule. It finally assigns numbers to vertices in each of the partitioned boxes location-wise so as to obtain the MinLA. Given m,n≥11, the size of boxes C₂,C₄,C₆ is increased by 2 until an increase in the MinLA is detected. This process repeats itself 4 times at maximum given m,n≤100. When tested to lattice in the range of 2≤n≤100, the proposed algorithm has proved its universal applicability to lattices of both m=n and m≠n. It has also obtained optimal results for 33×33 and 100×100 lattices superior to those obtained by existing algorithms. The minimum linear arrangement algorithm proposed in this paper, with its simplicity and outstanding performance, could therefore be also applied to the field of Very Large Scale Integration circuit where m,n are infinitely large.