• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.62-74
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• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.214-217
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• 2003

In this paper, we deal with implementing design for a correlator access code generator module which they are used for setting up a connection between units, a packet decision, a clock syncronization, by FPGA. The orrelator module which is composed of the Wallace Tree's CSA and threshold value decision device decides useful a packet and syncronizes a clock, after it correlates an input signal of 1 Mbps transmission rate by a sliding window. An access code generator module which is composed of a BCH (Bose-Chadhuri-Hocquenghem) cyclic encoder and control device was designed according as a four steps' generation process proposed in the bluetooth standard. The pseudo random sequence which solves syncronization problem saved a voluntary device Proposed the module was designed by VHDL. An simulation and test are inspected by Xilinx FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8A
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• pp.1441-1449
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• 2001

차세대 멀티미디어 이동통신인 IMT-2000의 규격에서는 3GPP와 3GPP2에서 모두 터보 코드를 채널 코덱으로 채택하고 있다. 그 중 3GPP 에서는 용도에 따라 길쌈부호와, 제한길이 4인 1/3 터보코드를 선택적으로 사용하도록 정의되어 있다. 터보코드는 복호기의 출력으로 경판정 복호 비트에 대한 신뢰도 값을 동시에 생성하여, 이를 이용한 반복복호로 우수한 BER 특성을 얻을 수 있어야 한다. 본 논문에서는 먼저 3GPP 규격의 터보 복호기에 적용할 수 있는 내부 복호기로서 SOVA 복호기를 설계하였다. 또한 터보 복호기에서의 연판정 출력값의 중요성을 감안하여, 누적메트릭 정규화에 있어서 신뢰도 값에 영향을 주지않는 구조를 제안하여 적용하였다. 본 연구에서는 효율적인 구조의 3GPP SOVA 복호기를 설계하기 위하여 C++를 이용하여 알고리즘에 대한 성능을 검증하였으며, 이를 기반으로 VHDL을 이용하여 복호기를 설계하였다. 마지막으로 Altera사의 EPF10K100GC503 FPGA를 이용하여 복호기를 하드웨어로 구현하였다.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.6
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• pp.625-630
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• 2014

Asynchronous digital circuits working in military and space environments are often subject to the adverse effects of radiation faults. In this paper, we propose a new hardening technique against radiation faults. The considered digital system has the structure of DMR (Double Modular Redundancy), in which two sub-systems conduct the same work simultaneously. Based on the output feedback, the proposed scheme diagnoses occurrences of radiation faults and realizes immediate recovery to the normal behavior by overriding parts of memory bits of the faulty sub-system. As a case study, the proposed control scheme is applied to an asynchronous dual ring counter implemented in VHDL code.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1137-1140
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• 1998

In this paper, we propose the new hardware architecture which implements the stereo matching algorithm using the dynamic programming method. The dynamic programming method is used in finding the corresponding pixels between the left image and the right image. The proposed MOEPE(Merged Odd-Even PE) architecture operates in the systolic manner and finds the disparities from the intensities of the pixels on the epipolar line. The number of PEs used in the MOEPE architecture is the number of the range constraint, which reduced the number of the necessary PEs dramatically compared to the traditional method which uses the PEs with the number of pixels on the epipolar line. For the normal method by 25 times. The proposed architecture is modeled with the VHDL code and simulated by the SYNOPSYS tool.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.5
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• pp.1036-1042
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• 2011

This paper presents an algorithm that conducts automatic memory scrubbing operated by dedicated hardwares. The proposed algorithm is designed so that it can scrub entire memory in a given scrub period, while minimally affecting the execution of flight softwares. The scrub controller is constructed in a form of state machines, which have two execution modes - normal mode and burst mode. The deadline event generator and period tick generator are designed in a separate way to support the behavior of the scrub controller. The proposed controller is implemented in VHDL code to validate its applicability. A simple version of the controller is also applied to mass memory modules used in STSAT-3.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.591-597
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• 2009

The problem of controlling a finite-state asynchronous sequential machine is examined. The considered machine is governed by input/output control, where access to the state of the machine is not available. In particular, disturbance inputs can infiltrate into the asynchronous machine and provoke unauthorized state transitions. The control objective is to use output feedback to compensate the machine so that the closed-loop system drive the faulty asynchronous machine from a failed state to the original one. Necessary and sufficient condition for the existence of appropriate controllers are presented in a theoretical framework. As a case study, the closed-loop system of an asynchronous machine with the proposed control scheme is implemented in VHDL code.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.10
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• pp.967-973
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• 2009

The model matching problem of asynchronous sequential machines is to design a corrective controller such that the stable-state behavior of the closed-loop system matches that of a prescribed model. In this paper, we address model matching when the external input set consists of controllable inputs and uncontrollable ones. Like in the frame of supervisory control of Discrete-Event Systems (DES), uncontrollable inputs cannot be disabled and must be transmitted to the plant without any change. We postulate necessary and sufficient conditions for the existence of a corrective controller that solves model matching despite the influence of uncontrollable events. Whenever a controller exists, the algorithm for its design is outlined. To illustrate the physical meaning of the proposed problem, the closed-loop system of an asynchronous machine with the proposed control scheme is implemented in VHDL code.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.63-66
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• 1999

Echo and near-end crosstalk(NEXT) can be generated in two-wire duplex transmission. In this paper investigates how to cancel echoes of high speed communication. A pipeline algorithm is used to remove the echoes that high speed communication. It is least mean squared(LMS) algorithm based on the relaxed look-ahead concept, is focused on the pipelined LMS, and its performance is compared to that of the serial LMS algorithm. And we design pipelined adaptive filtering. In advanced of the hardware implementation with VHDL code the performance of pipelined LMS algorithm is verified by the computer simulation.