• Journal of the Korean Society of Systems Engineering
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• v.17 no.2
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• pp.37-48
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• 2021

Improving the plant protection system against unforeseen changes/transients during operation is essential to maintain plant safety. Under this condition, it requires rapid and accurate signal processing. The use of an Intellectual Property (IP) core for floating point calculations for Safety Critical MMIS can make numerical computations easier and more precise, improving system accuracy. It can represent and manipulate rational numbers as well as a much broader range of values with dynamic range in nuclear power plant. Systems engineering approach (SE) is used through the development process, it helps to reduce complexity and avoid omissions and invalid assumptions as delivers a better understanding of the stakeholders needs. For the implementation on the FPGA target board, the 32-bit floating-point arithmetic with IEEE-754 standards has designed using Simulink model in Matlab for all operations of addition, subtraction, multiplication and division and VHDL code generated.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.463-467
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• 2004

A FTS (Flight Termination System) is a system that resides in a flying object such as a rocket, unmanned airplane, helicopter, missile, etc., receives commands from ground stations or detects coordinates automatically, and accomplishes a destruction command in case the object does not follow the presumed orbit. In this paper, we address the implementation of a communication modem for the FTS modem. We present general theory, simulation results using Matlab, and several results on the implementation using VHDL.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.113.3-113
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• 2001

In this paper, we have designed the VHDL module of DS/SS QPSK wireless modem processor for digital data communication. The spread spectrum method is used for modern processor, because this method guarantees good frequency efficiency and higher security. Also, it guarantees good performance in digital communication system under multi-path interferences. The differential encoder and decoder are used for simple circuit composition in the signal detection. For the synchronization of receiver, matched filter and power detector are used. And the IF modulation/demodulation of QPSK method is used in the digital level. The transmitter of VHDL modem processor consists of differential encoder, PN code generator, and QPSK ...

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.206-211
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• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.59-66
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• 1998

In this paper, the high-speed decoder for RS(Reed-Solomon) code, one of the most popular error correcting code, is implemented using VHDL. This RS decoder is designed in transform domain instead of most time domain. Because of the simplicity in structure, transform decoder can be easily realized VLSI chip. Additionally the pipeline architecture, which is similar to a systolic array is applied for all design. Therefore, This transform RS decoder is suitable for high-rate data transfer. After synthesis with FPGA technology, the decoding rate is more 43 Mbytes/s and the area is 1853 LCs(Logic Cells). To compare with other product with pipeline architecture, this result is admirable. Error correcting ability and pipeline performance is certified by computer simulation.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.67-70
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• 1999

DS-CDMA is used to widely spread spectrum for a cellular mobile digital communication that maximizing users- capacity at the limited frequency bandwidth, solving technical matters with the channel. Especially, the capability of a spread spectrum receiver relied on fast code acquisition time at the demodulation. In this paper, we considered that fast code acquisition time when a spread spectrum system is designed, and existed code acquisition system set up one code epoch on a position at initial processing, but the proposed code acquisition system improved that two code epoch are set up at the same time, therefore code acquisition time is diminished in effect. The structure modeling to VHDL language. Its synthesized the synthesized and, is implemented FPGA chip

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.763-770
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• 2006

In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.

• Journal of Digital Contents Society
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• v.7 no.3
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• pp.147-151
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• 2006

In recent years, the Internation Standard ISO/IEC 18000-6 is announced and a new scheme of Type C is added to conventional standard. Among the RFID systems the ISO/IEC 18000-6 standard is the most interesting to companies due to its potential market growth. The operating frequency is between 860-960 MHz, and three kinds of RFID system are included in the standard, i.e. type A, B and C. In this paper, we implemented the data frame of type C with baseband coding using VHDL. The data frame is encoded based on Miller code and FM0. We showed the implementation results with waveforms. The data frame was proved that it is properly implemented by the experiment of transmission and receiving operation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1073-1076
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• 1998

This paper describes implementation of a highlevel graphic design entry tool operating on X Window system The proposed design entry tool includes visual schematic entry, hierarchical modeling ability and VHDL source code generation. Experimental results show the efficiency of the proposed design system

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.277-280
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• 2000

In this paper, we designed a turbo decoder using VHDL. To maximize effective free distance of the turbo code, we implemented pseudo random interleaver. A MAP(Maximum a posteriori) decoder is used as a primimary decoder. We avoided multiplication by using lookup tables(ROM). We expect that this small-sized turbo decoder is suitable for mobile communication. We simulated turbo decoder with Altera MAX+PLUS II.