• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.1
• /
• pp.96-102
• /
• 1995

This paper presents the VHSIC Hardware Description Language(VHDL) implementation of the Fixed Point Covariance Lattice(FLAT) algorithm for an Linear Predictive Coding(LPC) analysis and its related algorithms, such as the forth order high pass Infinite Impulse Response(IIR) filter, covariance matrix calculation, and Spectral Smoothing Technique(SST) in the Vector Sum Exited Linear Predictive(VSELP) speech coder that has been Selected as the standard speech coder for the North America and Japanese digital cellular. Existing Digital Signal Processor(DSP) chips used in digital cellular phones are derived from general purpose DSP chips, and thus, these DSP chips may not be optimal and effective architectures are to be designed for the above mentioned algorithms. Then we implemented the VHDL code based on the C code, Finally, we verified that VHDL results are the same as C code results for real speech data. The implemented VHDL code can be used for performing logic synthesis and for designing an LPC Application Specific Integrated Circuit(ASOC) chip and DsP chips. We first developed the C language code to investigate the correctness of algorithms and to compare C code results with VHDL code results block by block.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.325-328
• /
• 2001

This paper describes a VHDL code coverage checker for If design and verification. Applying the verification coverage to IP design is a methodology rapidly gaining popularity. This enables the designers to improve the IP design quality and reduces the time-to-market by providing the Quantitative measure of simulation completeness and test benches. To support this methodology, a VHDL code coverage model was defined and the measurement tool was developed.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.12
• /
• pp.1-12
• /
• 1998

In this paper, a design and implementation of VHDL-to-C mapping in the VHDL compiler back-end is described. The analyzed data in an intermediate format(IF), produced by the compiler front-end, is transformed into a C-code model of VHDL semantics by the VHDL-to-C mapper. The C-code model for VHDL semantics is based on a functional template, including declaration, elaboration, initialization and execution parts. The mapping is carried out by utilizing C mapping templates of 129 types classified by mapping units and functional semantics, and iterative algorithms, which are combined with terminal information, to produce C codes. In order to generate the C program, the C codes are output to the functional template either directly or by combining the higher mapping result with intermediate mapping codes in the data queue. In experiments, it is shown that the VHDL-to-C mapper could completely deal with the VHDL analyzed programs from the compiler front-end, which deal with about 96% of major VHDL syntactic programs in the Validation Suite. As for the performance, it is found that the code size of VHDL-to-C is less than that of interpreter and worse than direct code compiler of which generated code is increased more rapidly with the size of VHDL design, and that the VHDL-to-C timing overhead is needed to be improved by the optimized implementation of mapping mechanism.

• Journal of the Korea Society for Simulation
• /
• v.10 no.1
• /
• pp.25-34
• /
• 2001

In this paper, we describe the generation method of interface logic which replace between IP & IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new asynchronous sequential "Waveform to VHDL" code creation algorithm by flow chart conversion : Wave2VHDL - if only mixed asynchronous timing waveform is presented the level type input and pulse type input for handshaking, we convert waveform to flowchart and then replace with VHDL code according to converted flowchart. Also, we confirmed that asynchronous electronic circuits are created by applying extracted VHDL source code from suggest algorithm to conventional domestic/abroad CAD Tool, Finally, we assured the simulation result and the suggest timing diagram are identical.

• Proceedings of the Korea Society for Simulation Conference
• /
• 2001.05a
• /
• pp.82-87
• /
• 2001

In this paper we described the generation method of interface logic which can be replace between IP and IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new \"Waveform Conversion Algorithm : Wave2VHDL\", if only mixed asynchronous timing waveform suggested which level type input and pulse type input for handshaking, we can convert waveform to flowchart and then replaced with VHDL code according to converted flowchart. Also, we assure that asynchronous electronic circuits for IP interface are generated by applying extracted VHDL source code from suggested algorithm to conventional domestic/abroad CAD Tool, and then we proved that coincidence simulation result and suggested timing diagram.g diagram.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.3C
• /
• pp.64-68
• /
• 2005

Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.

• Proceedings of the KAIS Fall Conference
• /
• 2003.06a
• /
• pp.250-252
• /
• 2003

본 논문에서는 콘벌루션 부호를 사용한 대역확산 방식의 디지틀 통신모뎀을 FPGA를 이용하여 설계 및 검증을 하였다. 대역확산 방식에서의 콘벌루tus부호기(K=3, R=1/2), PN code(128chip) generator와 비터비 디코더를 Xilinx사의 FPGA 디자인 툴인 Xilinx Foundations3.1을 사용하여 VHDL simulation과 timing simulation을 수행하였고, FPGA 회로설계 검증 장비인 EDA-Lab 3000 장비를 사용하여 Xilinx사의 SPARTAN2 2S100PQ208칩에 configuration 한 후 Agilent사의 1681A logic analyzer를 사용하여 설계된 회로의 동작을 검증하였다.

• Proceedings of the Korean Information Science Society Conference
• /
• 1999.10c
• /
• pp.54-56
• /
• 1999

현재 많은 내장형 시스템을 구현하기 위한 방법론으로 가상 프로토타입(VP)을 이용하고 있다. 본 논문에서는 가상 프로토타입을 이용하여 내장형 시스템의 설계 및 구현을 위해 사용되는 시스템 명세 언어인 SpecCharts로 명세된 시스템을 동기적 의미론에 만족하는 SpecCharts의 Subset을 규명하여 동기화 형태로 해당명세를 변환시키고 이로부터 synchronous VHDL 코드로 생성할 수 있는 방법을 설계하였다. 동기적 의미론을 만족시키기 위하여 비결정적인 추상적인 모델(NDAM)을 이용하여 SpecCharts로부터 VHDL ？로 변환하는 방법을 제시하고, 변환된 VHDL 코드를 동기적 VHDL 코드로 변환하기 위하여 W. Baker에 의해 규명된 동기적 VHDL subset 적용하여 synchronous VHDL 코드를 생성하는 방법을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.10B
• /
• pp.1458-1463
• /
• 2001

본 논문에서는 고밀도 광 기록 시스템에 적용이 가능한 코드율이 8/15이고, (d, $textsc{k}$)=(2, 15)인 새로운 변조 코드 체계에 대한 변조 코딩 방법을 VHDL로 구현하였다. 인코딩 방법은 크게 세 가지로 구분되어 진다. 먼저 입력 데이터를 복수개의 바이트 단위로 묶어서 블록을 정의하고, 이 블록의 입력 데이터를 변환 테이블을 이용해서 채널 데이터로 변환한 후, 머징 비트(merging bits)를 첨가하여 데이터를 전송한다. 위와 같은 코딩 방법을 적용하여 새롭게 개발한 변조 코드에 대해 모의 실험을 통한 성능을 분석한 후 VHDL로 구현하여 검증하였다.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.192-195
• /
• 2000

GSM(Global System for Mobile Communication) system which is being used in Europe is composed A3, A5 and A8 algorithms. In this paper we implement A3 algorithm using VHDL, and verify the design by simulation. The A3 algorithm is divided into 3 parts, the encryption part, in which F-function encrypts 64 bit block data；the key generation part, which produces 32 bit subkeys；the control part, which produces the control code.