• Proceedings of the Korea Information Processing Society Conference
• /
• 2003.05a
• /
• pp.23-26
• /
• 2003

본 논문은 웨이블릿 변환 과정을 통해서 분해한 영상을 Shapiro가 제안한 효율적인 영상 압축 방법인 EZW(Embedded Zerotree Wavelet)알고리즘을 하드웨어로 설계하였다. 이를 위한 하드웨어 구조를 제시하고 VHDL로 모델링 하여 FPGA를 통해 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.5
• /
• pp.133-142
• /
• 2004

Recently, the growth of Internet and a variety of multimedia services through Internet increasingly demands high-speed packet transmission, the new routing function, and QoS guarantee on conventional routers. Thus, a new switching mechanical called the MPLS(Multi-Protocol Label Switching), was proposed by IETF(Internet Engineering Task Force) as a solution to meet these demands. In addition the deployment of MPLS network supporting Differentiated Services is required. In this paper, we propose the architecture of the MPLS switch supporting Differentiated Services in the MPLS-based network. The traffic conditioner consists of a classifier, a meter, and a marker. The VOQ-PHB module, which combines input Queue with each PHB queue, is implemented to utilize the resources efficiently. It employs the Priority-iSLIP scheduling algorithm to support high-speed switching. We have designed and verified the new and fast hardware architecture of VOQ-PHB and the traffic conditioner for QoS and high-speed switching using NS-2 simulator. In addition, the proposed architecture is modeled in VHDL, synthesized and verified by the VSS analyzer from SYNOPSYS. Finally, to justify the validity of the hardware architecture, the proposed architecture is placed and routed using Apollo tool.

• The Journal of the Acoustical Society of Korea
• /
• v.24 no.7
• /
• pp.387-394
• /
• 2005

In this paper, we propose a new transmission technique of audio signals for the serial connection of the speakers of multiple-channel audio systems. Analog audio signals from a multi-channel audio system are converted into digital signals with signal processing steps and transferred to each speaker through a serial line. The signal processing steps contain data compression and packet generation in association with audio signal characteristics. Each speaker gets its corresponding digital audio signals from the transmitted packets and converts the signals into analog audio signals to make sounds with the speaker All the proposed functions in this paper are modeled in VHDL. implemented with FPGA chips, and tested for actual multi-channel audio systems.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.2
• /
• pp.46-53
• /
• 1999

In this paper, a packer is proposed for removing the bottle-neck effect and processing easy signal using a new algorithm with the operation frequency of 54MHz in processing HDTV video signal. To verify the performance of the proposed packer, DCT coefficient encoding block with ROM table using a combinational logic is designed and its output data are used as the input data of the packer.The proposed circuits, in this paper, are designed by using VHDL code and its modeling and simulation are performed with SYNOPSYS tool in $0.65{\mu}m$ design rule.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.11
• /
• pp.97-104
• /
• 2004

This paper proposes an efficient VLSI architecture of 9-7/5-3 Lifting DWT filters that is used by lossy or lossless compression of JPEG2000. The proposed architecture uses only internal line memories to compute Lifting-DWT operations and its PE(Processing Element) has critical path with 1 multiplier and 1 adder. To reduce the number of PE, we make the vertical filter that is responsible for the column operations of the first level perform both the row and column operations of the second and following levels. As a result, the architecture has smaller hardware cost compared to that of other architectures. It was modeled in RTL level using VHDL and implemented on Altera APEX 20K FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1C
• /
• pp.35-44
• /
• 2004

In this paper, we design an efficient VLSI architecture of entropy coding algorithm in JPEG2000. Entropy coder is a context-based binary arithmetic encoder, and composed of a Context Extractor(CE) and an Arithmetic Coder(AC). We speed-up CE by skipping no-operation bits in coding passes, and AC is to be performed based on MQ coder. Because of using Qe value associated with each allowed context and probability estimation, MQ coder is a multiplication free coder that reduces computation loads and makes simple the structure of arithmetic coder. We have developed and synthesized the VHDL models of CE and AC pairs using Xilinx FPGA technology. The proposed architecture operates up to 30MHz.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.1
• /
• pp.119-127
• /
• 1998

In this paper, the design of a VLSI-based multilayer neural network is presented, which can be used as a dedicated hardware for character-type segmentation and character-element recogniti on consuming large processing time in conventional software-based Hangul printed-character recognition systems. Also the architecture and its design of a neural coprocessor interfacing the neural network with a host computcr and controlling thc neural network are presented. The architecture, behavior, and performance of the proposed neural coprocessor are justified using VHDL modeling and simulation. Experimental results show the successful rates of character-type segmentation and character-element recognition is competitive to those of software-based Hangul printed-character recognition systems with retaining high-speed.

• The Journal of the Korea Contents Association
• /
• v.6 no.11
• /
• pp.225-234
• /
• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.38 no.6
• /
• pp.82-92
• /
• 2001

This paper describes implementation of an embedded 32-Bit RISC core for portable communication/information equipment, such as cellular phones, PDA(Personal Digital Assistants), notebook, etc. The RISC core implements the ARM$\circled$V 4 instruction set, operates with typical 5-stage pipeline. It supports Thumb code to improve the code density, and uses the dynamic power management method of pipeline registers. It was modeled and simulated in RTL level using VHDL, and verified with ARMulator of ADS (Arm Developer Suite) and had average CPI of 1.44. The core is synthesized automatically using the cell library based on $0.6{\mu}m$ CMOS 1-poly 3-metal CMOS technology. It consists of about 41,000 gates and the clock frequency is expected to be above 45 MHz.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.10 no.4
• /
• pp.3-11
• /
• 2000

In this paper, we design modular multiplication systolic array and exponentiation processor having n bits message black. This processor uses Montgomery algorithm and LR binary square and multiply algorithm. This processor consists of 3 divisions, which are control unit that controls computation sequence, 5 shift registers that save input and output values, and modular exponentiation unit. To verify the designed exponetion processor, we model and simulate it using VHDL and MAX+PLUS II. Consider a message block length of n=512, the time needed for encrypting or decrypting such a block is 59.5ms. This modular exponentiation unit is used to RSA cryptosystem.