• Title/Summary/Keyword: VHD

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Performance Improvement of the 2-phase Stepping Motor Driver with CPLD (CPLD를 이용한 2상 스테핑 모터 드라이버의 성능개선)

  • 오태석;전성구;김일환
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.53 no.9
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    • pp.615-621
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    • 2004
  • This paper describes the design of a 2-phase stepping motor driver using CPLD. The driver IC such as L297, which is mostly used has some difficulties in PWM current control because of the switching noise of power MOSFETs. The switching noise causes current ripple and acoustic noise. To reduce the switching noise, we designed a digital filter using VHDL. Also we designed constant current method for 1-2 phase(half step) excitation to reduce the torque ripple. Experimental results show the effectiveness of the proposed method. It is enabling further enhancements of stepping motor drive technology broadening the range of applications for the stepping motors.

A study on the Modeling and design of Parwan CPU using a VHDL (VHDL을 이용한 Parwan CPU의 Modeling과 Design)

  • 박두열
    • Journal of the Korea Society of Computer and Information
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    • v.7 no.2
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    • pp.19-33
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    • 2002
  • In this Paper, we described the Parwan CPU using a VHDL at the behavioral level and then described by connecting CPU components at the dataflow level. Finally, we simulated to verify of execution of a CPU processor using a test-bench method. A presented design method was to enable information exchange of design and representation of operation were very exact and simple. Also. a documentation of design was available and it was easy that verify a operation of designed processor. The behavioral description of VHDL aids designer as we verify our understanding of the designed system, while the dataflow description can be used to verify the bussing and register structure of the design.

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FPGA Implementation and Verification of A Pipelined 32-bit ARM Processor (파이프라인 방식의 32 비트 ARM 프로세서에 대한 FPGA 구현 및 검증)

  • Lee, Jongbok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.5
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    • pp.105-110
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    • 2022
  • Domestically, we are capable of designing high-end memory semiconductors, but not in processors, resulting in unbalance. Using Vivado as a development enivronment and implementing the processor on a Xilinx FPGA reduces time and cost dramatically. In this paper, the popular language VHDL which is widely used in Europe, universities, and research centers around the world for the digital system design is used for designing a pipelined 32-bit ARM processor, implemented on FPGA and verified by Integrated Logic Analyzer. As a result, the ARM processor implemented on FPGA could execute ARM instructions successfully.

The design of the POCSAG decoder using FPGA (FPGA를 이용한 POCSAG 복호기의 설계)

  • Lim, Jae-Young;Kim, Geon;Kim, Young-Jin;Kim, Ho-Young;Cho, Joong-hwee
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.7
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    • pp.269-277
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    • 1996
  • This paper has been presented a design of a POCSAG decoder in RT-level VHDL and implemented in a FPGA chip, and tested. In a single clock of 76.8KHz, the decoder receives all the data of the rate of 512/1200/2400bps and has maximum 2-own frames for service enhancement. To improve decoder performance, the decoder uses a preamble detection cosidering 9% frequency tolerance, a SCW detction and a ICW detection at each 4 bit. The decoder also corrects a address data and a message data up to 2 bits and proposes the PF (preamble frequency) error for saving battery. The decoder increases a battery life owing to turn off RF circuits when the preamble signal is detected with nises. The chip has been designed in RT-level VHdL, synthesized into logic gates using power view$^{TM}$ of viewlogic software. The chip has been implemented in an ALTERA EPF81188GC232-3 FPGA chip with 98% usability, and fully tested in shield room and field room. The chip has been proved that the wrong detection numbers of preamble of noises are significantly reduced in the pager system using PDI 2400 through the real field test. The receiving performance is improved by 20% of aaverage, compared with other existing systems.

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The Effect of the Global Timber Market on Global Warming when Climate Changes (기후변화의 영향을 받는 세계목재시장이 역으로 지구온난화에 미치는 영향)

  • Lee, Dug Man
    • Environmental and Resource Economics Review
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    • v.17 no.2
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    • pp.287-311
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    • 2008
  • This paper is designed to examine how the global timber market impacted by climate change would affect global warming through the carbon flux of forests. For this purpose, we integrated the modified TSM 2000 and the extended TCM in order to simulate the projection of net carbon release of forests from 1995 to 2085. On the basis of the simulation results under normal demand growth scenario, we identified that the global timber market impacted by climate change ameliorates the atmospheric carbon about 3.60% of carbon dioxide concentration in 1990 over 90 years. This implies that the global timber market impacted by climate change has a negative feedback effect on global warming over 90 years. For sensitivity analysis, we performed these simulation procedure under high demand growth scenario and very high demand growth scenario.

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An Innovative Solution for the Power Quality Problems in Induction Motor by Using Silica and Alumina Nano Fillers Mixed Enamel for the Coatings of the Windings

  • Mohanadasse, K.;Sharmeela, C.;Selvaraj, D. Edison
    • Journal of Electrical Engineering and Technology
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    • v.10 no.4
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    • pp.1621-1625
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    • 2015
  • Power quality has always been a concern of power engineers. Certainly an argument can be successfully made that most parts of power engineering have the ultimate objective to improve power quality. AC motors were widely used in industrial and domestic applications. Generally, AC motors were of two types: Induction and Synchronous motors. In motor many parameters like different load cycling, switching, working in hot weather and unbalances creates harmonics which creates major reasons for temperature rise of the motors. Due to high peak value of voltage, harmonics can weaken insulation in cables, windings and capacitors and different electronic components. Higher value of harmonics increase the motor current and decrease the power factor which will reduce the life time of the motor and increase the overall rating of all electrical equipments. Harmonics reduction of all the motors in India will save more power. Coating of windings of the motor with nano fillers will reduce the amount of harmonics in the motor. Based on the previous project works, actions were taken to use the enamel filled with various nano fillers for the coating of the windings of the different AC motors. Ball mill method was used to convert the micro particles of Al2O3, SiO2, TiO2, ZrO2 and ZnO into nano particles. SEM, TEM and XRD were used to augment the particle size of the powder. The synthesized nano powders were mixed with the enamel by using ultrasonic vibrator. Then the enamel mixed with the nano fillers was coated to the windings of the several AC motors. Harmonics were measured in terms of various indices like THD, VHD, CHD and DIN by using Harmonic analyzer. There are many other measures and indices to describe power quality, but none is applicable in all cases and in many instances, these indices may hide more than they show. Sometimes power quality indices were used as a basis of comparison and standardization. The efficiency of the motors was increased by 5 – 10 %. The thermal withstanding capacity of the motor was increased by 5º to 15º C. The harmonics of the motors were reduced by 10 – 50%.