• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Journal of Multimedia Information System
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• v.5 no.2
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

• Progress in Superconductivity
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• v.5 no.1
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• pp.45-49
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• 2003

We have designed and fabricated the single-layer high $T_{c}$ SQUID magnetometer consisting of a directly coupled grain boundary junction SQUID with an inductance of 100 pH and 16 nested parallel pickup coils with the outermost dimension of 8.8 mm ${\times}$ 8.8 mm. The magnetometer was formed from a YBCO thin film deposited on an STO(100) bicrystal substrate with a misorientation angle of $30^{\circ}$. The SQUID magnetometer was further improved by optimizing the multi-loop pickup coil design for use in unshielded environments. Typical characteristics of the dc SQUID magnetometer had a modulation voltage of 40 $\mu\textrm{V}$ and a white noise of $30fT/Hz^{1}$2/. The SQUID magnetometer exhibited a 1/f noise level at 10 Hz reduced by a factor of about 3 compared with that of the conventional solid type pickup coil magnetometers and a very stable flux locked loop operation in magnetically disturbed environments.s.

• The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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• v.12 no.3
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• pp.225-233
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• 2007

To verify which loop regions of 18S rRNA gene are suitable as species-specific genetic markers in ciliates, we analyzed the genetic variation of 18S rRNA gene among 9 Euplotes species (Hypotrichia : Ciliophora). In our result, no inter-specific variation was detected from V1, V3 and V5 regions, and the length of V7 and V8 are 44 bp and 79 bp, respectively, which are too short to make genetic marker. In contrast, V2 and V4 may be good candidate segments of species-specific diagnostic molecular markers because these two regions are most variable ($1.75{\sim}20.61%$) and showed good inter-specific phylogeny. Furthermore, the sequences of V2 and V4 are 123 bp and 306 bp, respectively in length which are enough to make species-specific marker.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.6
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• pp.570-579
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• 2009

In this paper, we presented a Vt-DRO with a wide electrical frequency tuning range, using open-loop gain method. The Vt-DRO was composed of 3-stages, resonator, amplifier and phase shifter. In order to satisfy an oscillation condition, we determined magnitude and phase of each stage. The measured S-parameter of cascaded 3-stages shows open-loop oscillation condition. Also, using measured open loop group delay, we derived the relation for electrical frequency tuning range. The Vt-DRO was implemented by connecting the input and the output of the designed open-loop and resulted in closed-loop. As a results, tuning-range of Vt-DRO is 82 MHz, which is close to the predicted results for tuning voltage 0${\sim}$10 V and shows linear frequency tuning at the center frequency of 5.3 GHz. The phase noise is -104 ${\pm}$1 dBc/Hz at 100 kHz offset frequency and power is 5.86${\pm}$1 dBm respectively.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.2
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• pp.93-101
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• 2017

This paper proposes an algorithm for adaptive loop filter (ALF) complexity reduction in the decoding process. In the original ALF algorithm, filtering for I frames is performed in the frame unit, and thus, all of the pixels in a frame are filtered if the current frame is an I frame. The proposed algorithm is designed on top of the local gradient calculation. On both the encoder side and the decoder side, homogeneous areas are checked and skipped in the filtering process, and the filter coefficient calculation is only performed in the inhomogeneous areas. The proposed algorithm is implemented in Joint Exploration Model (JEM) version 3.0 future video coding reference software. The proposed algorithm is applied for frame-level filtering and intra configuration. Compared with the JEM 3.0 anchor, the proposed algorithm has 0.31%, 0.76% and 0.73% bit rate loss for luma (Y) and chroma (U and V), respectively, with about an 8% decrease in decoding time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.331-338
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• 2014

A charge-pump circuit using a current-bypass technique, which suppresses charge sharing and reduces the sub-threshold currents, helps to decrease phase-locked loop (PLL) jitter without resorting to a feedback amplifier. The PLL shows no stability issues and no power-up problems, which may occur when a feedback amplifier is used. The PLL is implemented in 0.11-${\mu}m$ CMOS technology to achieve 0.856-ps RMS and 8.75-ps peak-to-peak jitter, which is almost independent of ambient temperature while consuming 4 mW from a 1.2-V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.352-358
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• 2016

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.