• KIEE International Transactions on Electrophysics and Applications
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• v.2C no.5
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• pp.253-257
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• 2002

A new Current-Controlled Driving Method that can drive AC PDPs with low voltage and high luminous efficiency for the sustaining period is presented. In this driving method, the voltage source is connected to a storage capacitor and the stored voltage is delivered to the panel through LC resonance. Thus, this driving method can drive the panel with a voltage source as low as about half of the voltage necessary in the conventional driving methods. The discharge current flowing into the AC PDP is limited in this method. Thus, the power consumption for the discharge is reduced and the discharge input power to output luminance efficiency is improved. Experimental results using this driving method showed that we could drive an AC PDP with a voltage source as low as 146V and that high luminous efficiency of 1.33 1m／W can be achieved.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1555-1557
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• 2001

To compare the lightning impulse measurement capabilities of high voltage laboratory, a lightning impulse voltage measuring system from HUT is circulated around the world. This paper presents test results after second round of this worldwide exercise. KERI's impulse voltage measuring system compared with the circulating reference measuring system from HUT at voltage levels of 80, 160, 240, 320 and 400 kV. Three impulse shapes were used, i.e. full smooth lightning impulse with both short (0.84 $\sim$ 0.95 ${\mu}s$) and long front (1.45 $\sim$ 1.56 ${\mu}s$), and chopped impulse with time to chopped impuse. Impulse peak value ($U_p$) and time parameters ($T_1$, $T_2$ and $T_c$) according to IEC 60060-1 were compared.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.358-358
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• 2010

To improve the programming/erasing speed and leakage current of multiple dielectric stack tunnel barrier engineering (TBE) Non-volatile memory, We propose a new concept called staggered structure of TBE memory. In this study, We fabricated staggered structure capacitor on $Si_3N_4$ stacked HfAlO and measured C-V curve that can observe tunneling characteristic of this device as various annealing temperature compared with that of single layer $SiO_2$ capacitor.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.38-43
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• 1994

GaAs and AlGaAs layers were grown by Molecular Beam Epitaxy (MBE) to fabricate hith performance GaAs MESFETs. Optimum growth temperatures were found to be 600$^{\circ}C$ from their Hall measurement data. MESFETs with the gate legth of 1${\mu}$m and the gate width of 100.mu.m were fabricated on the MBE-grown GaAs layters which has i-GaAs buffer layer and characterized. Knee volgate and mazimum transconductance of the devices were 1V, 224mS/mm, respectively. Cut-off frequency at on-wafer measuring pattern was measured to be 18 GHz. The MESFET with the 1${\mu}$m -thick i-Al$_{0.3}Ga_{0.7}$As buffer layer between nactive and i-GaAs was fabricated on order to reduce the leakage current which flows through the i-GaAs buffer layer. Its output resistance was 2.26 k${\Omega}$.mm which increased by a factor of 15 compared with the MESFET without i-Al$_{0.3}Ga_{0.7}$As buffer layer.

• Publications of The Korean Astronomical Society
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• v.7 no.1
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• pp.167-188
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• 1992

서울대 천문학과(SNU)의 Washington 측광계를 사용하여 관측한 자료와 ADC (Astronomical Data Center)의 자료를 분석함으로써 SNU Washington 측광계를 표준화 시켰다. SNU Washington 측광계중에서 C필터에 나타나는 적색광 누출은 V필터와의 결합을 통해 보정했으며, 그 최대값은 K0형에서 약 $0^{m}.14$까지 이른다. ADC의 자료분석 결과 G. K형 별들에 대해 중원소 측광지수와 중원소함량과 서로 잘 일치함을 알 수 있었고. 주계열성의 경우 온도 측광지수와 온도와는 좋은 관계를 보임을 알 수 있었다. 또한 ($M-T_2$)과 ($M-T_1$) 평면상에서는 중원소함량과 광도계급에 무관한 좋은 온도관계를 나타냄을 알았다. 그리고 이 측광계의 장점으로 나타난 CN지수와 CN 특이성과는 특별한 관계를 찾기가 어려웠고, 이 측광계만으로는 상도계급의 구분을 다른 측광계 만큼 분명하게 결정짓기가 어려웠다. 그러나 표면중력과이 측광계의 색지수와의 관계를 본 결과 초거성, 거성, 주계열성을 비교적 잘 구분해 낼 수 있었다.

• 한국전산유체공학회:학술대회논문집
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• 2010.05a
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• pp.28-31
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• 2010

In order to clarify the characteristics of power performance and uncertainty of a wind turbine, an investigation was performed in Hangyeong wind farm, Jeju island, Korea. Data were collected for 12 months from Feb. 2, 2008 to Jan. 1, 2009. This study was conducted on the base of the International standard, and observed the methods of mesurement and evaluation form IEC 61400-12. As a result, power performance curve was calculated by measured data and compared with the sixth unit of VESTAS V90-3.0MW in Hangyeong wind farms. In consequence of this paper, uncertainty was estimated from 7% to 14% on the range of the average wind speed from 4m/s to 11m/s.

• Proceedings of the KSME Conference
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• 2002.08a
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• pp.271-274
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• 2002

This paper is investigated construction of the Scramjet test facility and test method of Scramjet engine combustor model. Scramiet engine combustor model test was performed at Lab C-16BK CIAM (Central Institute of Aviation Motors) at Tyraevo in Moscow. The velocity of flow in the combustion chamber equal to Mach number 2.49 with single hole fuel spray nozzle injector and test duration equal to 7 seconds. Therefore In this paper is showed high altitude test method of Scramjet combustor model and the proper structure of combustor with single hole fuel spray nozzle.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.281-283
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• 1999

This topic presents an inductor short turn testing. From the rudimentary principles, the quality factor(Q) decreases due to inductor short turn. Frequency response varies because of the variation of circuit inductance and resistance. In general, short turn circuit testing is performed by comparing the ratio of an inductance and resistance of inductor in that particular circuit. An alternative method can be done by considering the response of second order circuit which can give both dynamic and static testing, whereas static testing give an error results not more than 2 turns. For dynamic testing, the result is more accurate, which can test fur the short turn number form 1 turn onward.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.914-917
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• 1999

The paper describes a 17 $\times$ 17-b multiplier using the Radix-4 Booth’s algorithm. which is suitable for 32-bit RISC/DSP microprocessors. To minimize design area and achieve improved speed, a 2-stage pipeline structure is adopted to achieve high clock frequency. Each part of circuit is modeled and optimized at the transistor level, verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, we lay it out in a 0.35 ${\mu}{\textrm}{m}$ 1-poly 4-metal CMOS technology and perform LVS test to compare the layout with the schematic. The simulation results show that maximum frequency is 330MHz under worst operating conditions at 55$^{\circ}C$ , 3V, The post simulation after layout results shows 187MHz under worst case conditions. It contains 9, 115 transistors and the area of layout is 0.72mm by 0.97mm.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.158-163
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• 1996

In the conventional GaAs MESFET circuit simulation, the DC and transient simulation results are often failed due to the discontrinuities of the first and second order derivatives arising from the use of separate C-V models in linear, satruration, and transition regions. In this paper, we propose a unified capacitance model for linear, transition, and saturation regions by using a unified channel length modulation effect that is derived by extending the channel length modulation effect in the saturation region to the linear region. Calculated resutls from the proposed capacitance model agree well with 2-D device simulation resutls. Thus, the proposed model is expected to be useful in circuit simulation.