• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.126-128
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• 2023

본 논문에서는 2-bit RISC-V 프로세서 상에서의 경량 블록 암호인 SPECK의 CTR 운용 모드에 대한 최적 구현을 제안한다. RISC-V 상에서의 SPECK 단일 평문과 2개의 평문에 대한 최적화와 고정된 논스 값을 사용하는 CTR 운용모드의 특징을 활용하여 일부 값에 대해 사전 연산을 하는 라운드 함수 최적화를 제안한다. 결과적으로, 레퍼런스 대비 제안된 기법은 단일 평문과 2개의 평문에 대해 각각 5.76배 2.24배 성능 향상을 확인하였으며, 사전 연산 기법을 적용하지 않은 최적 구현 대비 사전 연산 기법을 적용하였을 때, 1% 성능 향상을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.222-227
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• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.2
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• pp.128-133
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• 2008

This paper describes underwater discharge phenomena and breakdown characteristics in case that the standard lightning impulse voltage is injected to the needle and spherical electrodes installed in the hemisphere water tank. The objective of this work is to understand the basic features related to transient ground impedance against lightning surges. The discharge luminous images were observed and the dependence of breakdown voltage on the polarity of applied voltage and water resistivity were investigated. As a consequence, streamer corona is initiated at the tip of needle and spherical electrodes and is propagated toward grounded tank with stepwise extension. The breakdown voltage characteristics measured as a function of water resistivity showed V-shaped curves. Breakdown voltage and time curve of needle electrode is higher than that of spherical electrode.

• Progress in Medical Physics
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• v.6 no.1
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• pp.65-77
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• 1995

A new gamma camera using a-Si : H photodetectors has been designed for the imaging of heart and other small organs. In this new design the photomultiplier tubes and the position sensing circuitry are replaced by 2-D array of a-Si : H p-i-n pixel photode tectors and readout circuitry which are built on a substrate. Without the photomultiplier tubes this camera is light weight, hence can be made portable. To predict the characteristics and the performance of this new gamma camera we did Monte Carlo simulations. In the simulations 128${\times}$128 imaging array of various pixel sixes were used. $\^$99m/Tc(140keV)and $\^$201/Tl(70keV) were used as radiation sources. From the simulations we could obtain the resolution of the camera and ther overall system, and the blurring effects due to scattering in the phantom. Using the Wiener filter for image processing, restoration of the blurred image could be achieved. Simulation results of a-Si : H based gamma camera were compared with those of a conwentional gamma camera.

• Journal of Sensor Science and Technology
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• v.18 no.2
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• pp.128-134
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• 2009

Integrated circuit of a new neuron chain with a synapse function for Hodgkin-Huxley model which is a good electrical model about a real biological neuron is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Pulse type neuron chain consist of series connected current controlled single neurons through synapses. For the realization of the single neuron, a pair of voltage mode oscillators using operational transconductance amplifiers and capacitors is used. The synapse block which is a connection element between neurons consist of a voltage-current conversion circuit using current mirror. SPICE simulation results of the proposed circuit show 160 mV amplitude pulse output and propagation of the signal through synapses. Measurements of the fabricated pulse type neuron chip in condition of ${\pm}2.5\;V$ power supply are shown and compared with the simulated results.

• The Bulletin of The Korean Astronomical Society
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• v.36 no.2
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• pp.128.2-128.2
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• 2011

Experiments to study high-energy cosmic rays (CRs) employ Monte Carlo codes for extensive air shower (EAS) simulations to figure out the properties of CRs. COSMOS and CORSIKA among EAS simulation codes are currently being used to analyze the data of the Telescope Array experiment. We have generated a library of about 10,000 simulated EASs with the primary energy ranging from $10^{18.5}eV$ to $10^{20}eV$ and the zenith angle of primary particles ranging from 0 to 45 degree for proton and iron primaries. We have compared the results predicted by CORSIKA and COSMOS under the same condition. In this talk, we show the differences in the energy spectra at the ground, the longitudinal shower profile as a function of atmospheric depth, the Calorimetric energy, and the Xmax distribution. We also discuss the lateral distribution function obtained from GEANT4 simulations which is being used to measure the detector response.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1210-1217
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• 2004

LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS ＆ 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Journal of Dairy Science and Biotechnology
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• v.35 no.4
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• pp.249-254
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• 2017

The purpose of this study was to investigate the acid tolerance, bile acid tolerance, and fermentation activity of lactic acid bacteria isolated from Kimchi in the presence of hydrolysates of whey protein concentrate. Kimchi isolates DK109, DK119, DK121, DK128, DK211, DK212, and DK215, which were identified as Lactobacillus sp., and L. casei DK128 showed the highest acid and bile acid tolerance. To produce whey hydrolysates, enzymes were added to a 10% (w/v) whey protein concentrate (WPC) solution at 1:50 (w/v, protein). The viabilities of the DK strains were determined in the presence of low pH and bile salts. Then, yogurt was produced via fermentation with L. casei DK128, an isolate from Kimchi, in the presence of the following additives: CPP, WPC, and WPC hydrolysates (WPCH) generated by alcalase (A) or neutrase (N). The produced yogurts were subjected to various analyses, including viable cell counts (CFU/mL), pH, titratable activity, and sensory testing. After 8 h of fermentation, the pH and titratable activity values of all test samples were 4.2 and 0.9, respectively. The viable counts of LAB were $3.49{\times}10^8$, $5.72{\times}10^8$, $7.01{\times}10^8$, and $6.97{\times}10^8$, for the Control, CPP, A, and N samples, respectively. These results suggest that whey proteins have potential as dietary supplements in functional foods and that WPCH could be used in yogurt as a low-cost alternative to CPP.