• Journal of Power Electronics
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• v.7 no.3
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• pp.213-221
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• 2007

A digital state feedback control method for the current mode control of DC-DC converters is proposed in this paper. This approach can precisely achieve interleaved current sharing among the converter modules. As the controller design and system analysis are performed in the time domain, the proposed method can easily satisfy the required converter specification by using the pole placement technique. The digital state feedback controller in the continuous and discrete time domain is derived for the robust tracking control. For the verification of the proposed control scheme, a parallel module bi-directional converter in a prototype 42V/14V hybrid automotive power system, which is a design example in the continuous time domain, and a parallel module buck converter, which is a design example in the discrete time domain, are implemented using a TMS320F2812 digital signal processor (DSP).

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.10
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• pp.15-27
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• 1997

Quasti-static cutting force variations in milling process are measured indirectly using spindle motor current. Quasi-static sensitivity of the spindle motor current is higher than that of the feed motor current. Magnitude of the spindle motor current is independent of cutting direction. The linear relationship between the cutting force and the spimdle motor RMS current at various spindle rotational speed is obtained. Frequency/ Voltage(F/V) converter voltage is measured to identify the spindle speed and to determine the cutting force at various spindle speeds. Overload on the tool during milling process can be detected using the proposed indirect cutting force measurement. Based on these measurements, cutting force is regulated at a constant level by feedrate control.

• 전기의세계
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• v.30 no.7
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• pp.454-459
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• 1981

The aim of study in this paper is that in a system drive of the converter-inverter fed induction motor, the minimum input power can be maintained by control the voltage and frequency of the motor. In theoretical and experiment results describtion motor efficiency is improved by properly varying the ratio v/f. At lightly load condition, for example its efficiency was improved from 44% to 66% as the ratio of v/f varied from 1 to 0.57.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.168-168
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• 2004

본 논문은 헤테로다인 간섭계를 이용한 레이저 진동 측정기에 대해 기술하고 있다. 상용 레이저 진동 측정기가 대부분 AOM을 이용하여 주파수 천이를 일으키는 반면, 본 연구에서는 Zeeman 안정화 He-Ne 레이저를 사용하므로써, 서로 다른 주파수를 가지는 레이저를 동시에 얻을 수 있었다. 따라서, Zeeman 안정화 He-Ne 레이저를 사용하는 진동측정기의 경우 간섭계 구성을 위해 사용되는 비용을 현저히 줄일 수 있다. 또한, AOM의 고주파 신호를 처리하기 위해서는 RE 대역의 신호처리 회로 설계가 필요하지만, Zeeman 안정화 레이저의 주파수 천이가 낮으므로, 제안된 진동측정기의 신호처리가 용이하다.(중략)

• Journal of Power Electronics
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• v.14 no.1
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• pp.1-10
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• 2014

This paper proposes a high-efficiency supercapacitor charger. Conventional two-switch forward converter can be used for charging supercapacitors. However, the efficiency of conventional converters is low because of their switching losses. This study presents a high-efficiency two-switch forward converter for supercapacitor chargers. The proposed converter improves power efficiency by 4 %, from 89 % to 93 %. The proposed converter has the advantages of reduced switch voltage stresses and minimized circulating current when compared to other converter topologies. The performance of the proposed converter is evaluated by experimental results using a 300 W prototype circuit for a 54-V, 35-F supercapacitor bank.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.13 no.4
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• pp.14-20
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• 1999

This paper presents a design techniques for an electronic ballast of HID lamps. An electronic ballast for HID lamps usually employs a high-frequeocy resonant inverter and voltage-to-frequency converter to control the outpIt and a half-bridge and series resonant circuit are chosen for the ballast First, to design PI controller, the inverter with V/F converter is modeled with a transfer function and the controller PI gains are determined. This paper shows that an integral controller is only needed to control the current. Second, a se1f-feedback controller is proposed. This structure, simple and robust, is analyzed and a feedback gain is determined by using the inverter model. Experirrental system is built with a commercial 250W high pressure sodium lamp and the results show a validity of the proposed ballast and the total efficiency is increased by 5%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).