• Journal of applied mathematics & informatics
• /
• v.31 no.1_2
• /
• pp.119-130
• /
• 2013

In this paper, we obtain some generalized symmetry identities involving a unified class of polynomials related to the generalized Bernoulli, Euler and Genocchi polynomials of higher-order attached to a Dirichlet character. In particular, we prove a relation between a generalized X version of the power sum polynomials and this unified class of polynomials.

• Proceedings of the KIPE Conference
• /
• 1998.11a
• /
• pp.49-54
• /
• 1998

This paper describes a simulation model to analyze the dynamic performance of Unified Power Flow Controller, which adjust flexibly the active and reactive power flow through the ac transmission line. The basic operation was analyzed in detail using equivalent circuits and the design of control system was developed using vector control method. A simulation model with EMTP code was conceived to evaluate the performance of the Unified power Flow Controller. The simulation results show that the developed simulation model is very effective to analyze the dynamic performance of the Unified Power Flow Controller.

• Proceedings of the KIEE Conference
• /
• 2002.07a
• /
• pp.419-421
• /
• 2002

This paper presents a methodology for the application of Unified Modeling Language (UML) to develop the new load management system. Development of new load management system in competitive electricity market is very complex since it requires too much data of power system. For the efficient and flexible design to develop of new load management system, a UML approach in applied which is composed of a class diagram, package diagram using Rational Rose Unified Process.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.3
• /
• pp.213-223
• /
• 2013

A unified channel thermal noise model valid in all operation regions is presented for short channel MOS transistors. It is based on smooth interpolation between weak and strong inversion models and consistent physical model including velocity saturation, channel length modulation, and carrier heating. From testing for noise benchmark and comparing with published noise data, it is shown that the proposed noise model could be useful in simulating the MOSFET channel thermal noise in all operation regions.

• 제어로봇시스템학회:학술대회논문집
• /
• 1992.10a
• /
• pp.912-916
• /
• 1992

In this paper we investigate the connection between the continuous-time FIR(finite impulse response) filter and the corresponding discrtet-time FIR filter with fast sampling. The interconnection is established by formulating the discrete-time case using delta operators which has superior numerical properties in discretizing prcedure. The aim of this paper is to present a unified FIR filter using the .delta.-operator and to show that, as sampling interval .DELYA. aperator to zero, the results of this filter converge to the corresponding continuous-time reuslts, which implies that the unified FIR filter unifies continous-time FIR filter and discrtet-time FIR filter.

• Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
• /
• 2010.04a
• /
• pp.141-142
• /
• 2010

In Korea, land mapping and ocean charting have traditionally different vertical datum for purposes. Ministry of Land, Transportation and Maritime Affairs(MLTM) has promoted National Unified Vertical Datum project in 2009. In this study the development of National Unified Vertical Datum is proposed.

• Bulletin of the Korean Mathematical Society
• /
• v.58 no.2
• /
• pp.315-326
• /
• 2021

Korobov type polynomials are introduced and extensively investigated many mathematicians ([1, 8-10, 12-14]). In this work, we define unified Apostol Korobov type polynomials and give some recurrences relations for these polynomials. Further, we consider the q-poly Korobov polynomials and the q-poly-Korobov type Changhee polynomials. We give some explicit relations and identities above mentioned functions.

• Journal of Electrical Engineering and Technology
• /
• v.7 no.4
• /
• pp.570-575
• /
• 2012

In a wireless communication RF transmitter, the output of a quadrature modulator (QM) is distorted by not only the linear imperfection features such as in/quadrature-phase (I/Q) input gain imbalance, local phase imbalance, and local gain imbalance but also the nonlinear imperfection features such as direct current (DC) offset and mixer nonlinearity related to in-band spurious signal. In this paper, we propose the unified QM model to analyze the combined effects of the linear and nonlinear imperfection features on the performance of the QM. The unified QM model consists of two identical nonlinear systems and modified I/Q inputs based on the two-port nonlinear mixer model. The unified QM model shows that the output signals can be expressed by mixer circuit parameters such as intercept point and gain as well as the imperfection features. The proposed approach is validated by not only simulation but also measurement.

• Journal of Institute of Control, Robotics and Systems
• /
• v.9 no.5
• /
• pp.354-360
• /
• 2003

For the convenient use of high performance microprocessor in motor control, peripheral devices are needed for converting its control signals to compatible ones for motor drive. Customized devices are not plentiful far these purposes and their functions do not usually satisfied designers specification. The designers used to implement these functions on FPGA or CPLD using hardware description language. Then, in this case unessential programs are needed for control the peripherals. In this paper, a unified device model that links peripheral devices, including especially the pulse width modulation controller and the quadrature encoder interface device, to an interrupt controller is proposed. Advanced functions of peripherals could be achieved by this model and unessential programs can be simplified. Block diagrams and flowcharts are presented to illustrate the advanced functions. This unified device was designed using VHDL. The simulation results were presented to demonstrate the effectiveness of the proposed scheme.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.2
• /
• pp.162-167
• /
• 2012

This paper describes the design of a high-performance unified SVM classifier circuit. The proposed circuit supports both linear and non-linear SVM classifications. In order to ensure efficient classification, a 48x96 or 64x64 sliding window with 20 window strides is used. We reduced the circuit size by sharing most of the resources required for both types of classification. We described the proposed unified SVM classifier circuit using the Verilog HDL and synthesized the gate-level circuit using 65nm standard cell library. The synthesized circuit consists of 661,261 gates, operates at the maximum operating frequency of 152 MHz and processes up to 33.8 640x480 image frames per second.