JSTS:Journal of Semiconductor Technology and Science

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A Unified Channel Thermal Noise Model for Short Channel MOS Transistors

  • Yu, Sang Dae (School of Electronics Engineering, Kyungpook National University)
  • Received : 2012.09.22
  • Accepted : 2013.01.28
  • Published : 2013.06.30
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Abstract

A unified channel thermal noise model valid in all operation regions is presented for short channel MOS transistors. It is based on smooth interpolation between weak and strong inversion models and consistent physical model including velocity saturation, channel length modulation, and carrier heating. From testing for noise benchmark and comparing with published noise data, it is shown that the proposed noise model could be useful in simulating the MOSFET channel thermal noise in all operation regions.

Keywords

References

  1. Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor. Oxford University Press, 2011.
  2. S. D. Yu, "Design of CMOS op amps using adaptive modeling of transistor parameters," Journal of Semiconductor Technology and Science, vol. 12, pp. 75-87, Mar. 2012. https://doi.org/10.5573/JSTS.2012.12.1.75
  3. C. H. Chen and M. J. Deen, "Channel noise modeling of deep submicron MOSFETs," IEEE Trans. Electron Devices, vol. 49, pp. 1484-1487, Aug. 2002. https://doi.org/10.1109/TED.2002.801229
  4. K. Han, H. Shin, and K. Lee, "Analytical drain thermal noise current model valid for deep submicron MOSFETs," IEEE Trans. Electron Devices, vol. 51, pp. 261-269, Feb. 2004. https://doi.org/10.1109/TED.2003.821708
  5. S. Asgaran, M. J. Deen, and C. H. Chen, "Analytical modeling of MOSFETs channel noise and noise parameters," IEEE Trans. Electron Devices, vol. 51, pp. 2109-2114, Dec. 2004. https://doi.org/10.1109/TED.2004.838450
  6. A. J. Scholten, L. F. Tiemeijer, R. van Langevelde, R. J. Havens, A. T. A. Zegers-van Duijnhoven, and V. C. Venezia, "Noise modeling for RF CMOS circuit simulation," IEEE Trans. Electron Devices, vol. 50, pp. 618-632, Mar. 2003. https://doi.org/10.1109/TED.2003.810480
  7. A. S. Roy and C. C. Enz "An analytical thermal noise model of the MOS transistor valid in all modes of operation," Proc. of the Int. Conf. on Noise and Fluctuations, vol. 780, pp. 741-744, Sep. 2005.
  8. Z. Li, J. Ma, Y. Ye, and M. Yu, "Compact channel noise models for deep-submicron MOSFETs," IEEE Trans. Electron Devices, vol. 56, pp. 1300- 1308, June 2009. https://doi.org/10.1109/TED.2009.2018160
  9. Y. Cheng, M. C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P. K. Ko, and C. Hu, "A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation," IEEE Trans. Electron Devices, vol. 44, pp. 277-287, Feb. 1997. https://doi.org/10.1109/16.557715
  10. D. P. Triantis, A. N. Birbas, and D. Kondis, "Thermal noise modeling for short-channel MOSFET's," IEEE Trans. Electron Devices, vol. 43, pp. 1950-1954, Nov. 1996. https://doi.org/10.1109/16.543032
  11. C. C. Enz and E. A. Vittoz, Charge-based MOS Transistor Modeling. John Wiley & Sons, 2006.
  12. A. van der Ziel, Noise in Solid State Devices and Circuits. John Wiley & Sons, 1986.
  13. M. Lundstrom, Fundamentals of Carrier Transport. Addison-Wesley, 1990.
  14. A. S. Roy and C. C. Enz, "Compact modeling of thermal noise in the MOS transistor," IEEE Trans. Electron. Devices, vol. 52, pp. 611-614, Apr. 2005. https://doi.org/10.1109/TED.2005.844735
  15. N. Arora, MOSFET Models for VLSI Circuit Simulation. Springer-Verlag, 1993.
  16. J. P. Nougier, "Fluctuations and noise of hot carriers in semiconductor materials and devices," IEEE Trans. Electron. Devices, vol. 41, pp. 2034- 2049, Nov. 1994. https://doi.org/10.1109/16.333821
  17. M. A. Omar and L. Reggiani, "Drift and diffusion of charge carriers in silicon and their empirical relation to the electric field," Solid-State Electronics, vol. 30, pp. 693-697, Jul. 1987. https://doi.org/10.1016/0038-1101(87)90106-7
  18. Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, and P. K. Ko, "Threshold voltage model for deep-submicrometer MOSFET's," IEEE Trans. Electron. Devices, vol. 40, pp. 86-95, Jan. 1993. https://doi.org/10.1109/16.249429
  19. S. Andersson and C. Svensson, "Direct experimental verification of shot noise in short channel MOS transistors," Electronics Letters, vol. 41, pp. 869-871, Jul. 2005. https://doi.org/10.1049/el:20051474
  20. C. C. Enz, F. Krummenacher, and E. A. Vittoz, "An analytical MOS transistor model valid in all regions of operation and dedicated to lowvoltage and low-current applications," Analog Integrated Circuits and Signal Processing, vol. 8, pp. 83-114, July 1995. https://doi.org/10.1007/BF01239381
  21. S. H. Jen, B. J. Sheu, and Y. Oshima, "A unified approach to submicron DC MOS transistor modeling for low-voltage ICs," Analog Integrated Circuits and Signal Processing, vol. 12, pp. 107- 118, Feb. 1997. https://doi.org/10.1023/A:1008212908346
  22. J. Jeon, B.-G. Park, J. D. Lee, and H. Shin, "Analytical noise parameter model of short-channel RF MOSFETs," Journal of Semiconductor Technology and Science, vol. 7, pp. 88-93, June 2007. https://doi.org/10.5573/JSTS.2007.7.2.088
  23. F. Bonani and G. Ghione, Noise in Semiconductor Devices. Springer-Verlag, 2001.
  24. A.-S. Porret and C. C. Enz, "Non-quasi-static (NQS) thermal noise modelling of the MOS transistor," IEE Proc. Circuits Devices Syst., vol. 151, pp. 155-166, Apr. 2004. https://doi.org/10.1049/ip-cds:20040436
  25. J.-S. Goo, C.-H. Choi, F. Danneville, E. Morifuji, H. S. Momose, Z. Yu, H. Iwai, T. H. Lee, and R. W. Dutton, "An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs," IEEE Trans. Electron. Devices, vol. 47, pp. 2410-2419, Dec. 2000. https://doi.org/10.1109/16.887030
  26. R. P. Jindal, "Distributed substrate resistance noise in fine-line NMOS field-effect transistors," IEEE Trans. Electron. Devices, vol. 32, pp. 2450-2453, Nov. 1985. https://doi.org/10.1109/T-ED.1985.22294
  27. J.-S. Goo, S. Donati, C.-H. Choi, Z. Yu, T. H. Lee, and R. W. Dutton, "Impact of substrate resistance on drain current noise in MOSFETs," in Proc. Int. Conf. SISPAD, pp. 182-185, Sep. 2001.
  28. C. Enz, "An MOS transistor model for RF IC design valid in all regions of operation," IEEE Trans. Microwave Theory Tech., vol. 50, pp. 342- 359, Jan. 2002. https://doi.org/10.1109/22.981286
  29. B. Razavi, R.-H. Yan, and K. F. Lee, "Impact of distributed gate resistance on the performance of MOS devices," IEEE Trans. Circuits and Systems I, vol. 41, pp. 750-754, Nov. 1994. https://doi.org/10.1109/81.331530
  30. E. Abou-Allam and T. Manku, "A small-signal MOSFET model for radio frequency IC applications," IEEE Trans. Computer-Aided Design of Integr. Circuits and Syst., vol. 16, pp. 437-447, May 1997. https://doi.org/10.1109/43.631207
  31. C. Jungemann, T. Grasser, B. Neinhuus, and B. Meinerzhagen, "Failure of moments-based transport models in nanoscale devices near equilibrium," IEEE Trans. Electron. Devices, vol. 52, pp. 2404-2408, Nov. 2005. https://doi.org/10.1109/TED.2005.857184
  32. G. D. J. Smit, A. J. Scholten, R. M. T. Pijper, R. van Langevelde, L. F. Tiemeijer, and D. B. M. Klaassen, "Experimental demonstration and modeling of excess RF noise in sub-100-nm CMOS technologies," IEEE Electron Device Lett., vol. 31, pp. 884-886, Aug. 2010. https://doi.org/10.1109/LED.2010.2051132
  33. The Mosis Service, http://www.mosis.com/requests /test-data, Dec. 2012.
  34. A. J. Scholten, R. van Langevelde, L. F. Tiemeijer, and D. B. M. Klaassen, "Compact modeling of noise in CMOS," Proc. of the IEEE Custom Integrated Circuits Conference, pp. 711-716, Sep. 2006.
  35. W. Liu, et al., BSIM3v3.3 MOSFET Model User's Manual. University of California, Berkeley, 2005.
  36. Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User's Guide. Kluwer Academic Publishers, 1999.

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