• Title/Summary/Keyword: Ultra-weight algorithm

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An Effective Cell Scheduling Algorithm for Input Queueing ATM Switch (입력단 큐잉 방식의 ATM 스위치를 위한 효율적 셀 중재 방식에 관한 연구)

  • 김용웅;원상연;박영근
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.1A
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    • pp.122-131
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    • 2000
  • In this paper, we propose a cell scheduling algorithm for input queueing ATM switch. The input queueing architecture is attractive for building an ultra-high speed ATM (Asynchronous Transfer Mode) switch. We proposea WMUCS (Weighted Matrix Unit Cell Scheduler) based on the MUCS which resolves HOL blocking and outputport contention. The MUCS algorithm selects an optimal set of entries as winning cells from traffic matrix (weightmatrix). Our WMUCS differs from the MUCS in generating weight matrices. This change solves the starvationproblem and it reduces the cell loss variance. The performance of the proposed algorithm is evaluated by thesimulation program written in C++. The simulation results show that the maximum throughput, the average celldelay, and the cell loss rate are significantly improved. We can see that the performance of WMUCS is excellentand the cost-effective implementation of the ATM switch using proposed cell scheduling algorithm.

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Selective-Weighted Energy Detector(S-WED) and Synchronization algorithm for IR-UWB systems (IR-UWB 시스템을 위한 선택적 가중치 결합 에너지 검출기(S-WED)와 동기 알고리즘)

  • Ji, Sinae;Kim, Jaeseok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.3-9
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    • 2013
  • This paper proposes a selective-weighted energy detection (S-WED) and a synchronization algorithm appropriate for it in IR-UWB system. Energy detectors that are practical in terms of implementation are employed widely for noncoherent reception in IR-UWB systems. However, they show low performance due to using the energy samples captured at symbol rate. For this reason, weighted energy detectors are developed to improve the performance of EDs. Hence, for WED, not only synchronization but also the weight coefficients are needed to be obtained prior to data detection. Meanwhile, the optimal weighting coefficients of WEDs are known to be energy values. Therefore, synchronization and the weighting coefficients can be obtained simultaneously. This paper proposes an S-WED and a simple synchronization algorithm for it in which sub-intervals having energies under a certain level are excluded in energy accumulation resulting in a simpler WED with a bit performance increase in low SNR region. The proposed algorithm is verified through simulations using the preamble symbol and channel models defined in the IEEE 802.15.4a.

A Study on the Throughput Enhancement in Software Implementation of Ultra Light-Weight Cryptography PRESENT (초경량 암호 PRESENT의 소프트웨어 구현 시 처리량 향상에 대한 연구)

  • Park, Won-kyu;Cebrian, Guillermo Pallares;Kim, Sung-joon;Lee, Kang-hyun;Lim, Dae-woon;Yu, Ki-soon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.42 no.2
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    • pp.316-322
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    • 2017
  • This paper suggests an efficient software implementation of lightweight encryption algorithm PRESENT which supports for secret key lengths of 80-bits. Each round of PRESENT is composed of the round key addition, substitution, and permutation and is repeated 31 times. Bo Zhu suggested combined substitution and permutation for efficient operation so that encryption throughput has been increased 2.6 times than processing substitution and permutation at separate times. The scheme that suggested in this paper improved the scheme of Bo Zhu to reduce the number of operation for the round key addition, substitution, and permutation. The scheme that suggested in this paper has increased encryption throughput up to 1.6 times than the scheme of Bo Zhu but memory usage has been increased.

A Study on the DBS Receive Tracking Antenna Apparatus on a Ship by the Az/El Mount (Az/El 마운트에 의한 선박용 DBS 수신추적안테나 장치에 관한 연구)

  • 최조천;양규식
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.1 no.2
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    • pp.209-220
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    • 1997
  • DBS offers actual services to mass-media and communication system of very broad region in information society. Especially, the DBS is the only system to access TV broadcasting service on a sailing ship. But the ship's DBS receiver is required a complex antenna tracking system because ships are under complex moving such as pitch, roll, and yaw etc. This study is motivated to develop a tracking antenna system to receive the koreasat on small silo ship. Therefore, this system is researched to small size, light weight, simple operation, and low cost of the product. The mount structure have been a compact size and easy operation to the Az/El 2-axis type which is operated by step motor. And it is very useful on a ship in the around sea of korean peninsula. The antenna has a plate type of micro-strip array, and is a domestic production. The vibration sensor is selected to gyro sensor of ultra-sonic rate type for ship's moving control. Tracking method is used the step-tracking algorithm, and the ship's moving compensation is adapted to the closed loop control method by ship's moving detection of gyro sensor. Tracking test is operated by the ship's moving simulator, we examined the actual receiving state on sailing shipboard in the near sea of korean peninsular.

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Low-cost AES Implementation for RFID tags (RFID 태그를 위한 초소형 AES 연산기의 구현)

  • Koo, Bon-Seok;Ryu, Gwon-Ho;Yang, Sang-Woon;Chang, Tae-Joo;Lee, Sang-Jin
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.16 no.5
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    • pp.67-77
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    • 2006
  • Radio Frequency IDentification (RFID) will soon become an important technology in various industries. Therefore, security mechanisms for Rm systems are emerging crucial problems in RFID systems. In order to guarantee privacy and security, it is desirable to encrypt the transferred data with a strong crypto algorithm. In this paper, we present the ultra-light weight Advanced Encryption Standard (AES) processor which is suitable for RFID tags. The AES processor requires only 3,992 logic gates and is capable of both 128-bit encryption and decryption. The processor takes 446 clock cycles for encryption of a 128-bit data and 607 clock cycles for decryption. Therefore, it shows 55% improved result in encryption and 40% in decryption from previous cases.