• Proceedings of the Korea Information Processing Society Conference
• /
• 2013.05a
• /
• pp.501-503
• /
• 2013

This project presents a concept of mobile robots using prototypes, computing proposal oriented to embedded systems implementation. We implement our system using GPS module, Ultrasonic sensor(range sensors), H-bridge dual stepper control, DTMF(Dual-tone Multi-Frequency ) and LCD module. In this paper we construct a mechanical simple mobile robot model, which can measure the distance from obstacle with the aid of sensor and should able to control the speed of motor accordingly. Modules were interfaced with FPGA(Field Programmable Gate Array) controller for hardware implementation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.1
• /
• pp.20-26
• /
• 2021

Recent systems contain hardware and software components together for faster execution speed and less power consumption. In conventional hardware and software co-design, the ratio of software and hardware was divided by the designer's empirical knowledge. To find optimal results, designers iteratively reconfigure accelerators and applications and simulate it. Simulating iteratively while making design change is time-consuming. In this paper, we propose a hardware and software co-design platform for energy-efficient FPGA accelerator design. The proposed platform makes it easy for designers to find an appropriate hardware ratio by automatically generating application program code and hardware code by parameterizing the components of the accelerator. The co-design platform based on the Vitis unified software platform runs on a server with Xilinx Alveo U200 FPGA card. As a result of optimizing the multiplication accelerator for two matrices with 1000 rows, execution time was reduced by 90.7% and power consumption was reduced by 56.3%.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.1
• /
• pp.311-323
• /
• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.5
• /
• pp.1240-1252
• /
• 1996

In this paper we propose a layout editor for the functional module generation in the Sea-of Gates(SOG) lay-out style. The proposed layout editor provides interactive was of designing a functional module to the designer so that the layout result is very satisfiable. Especially, the editor is independent on the shape of the basic cells in the gate array template, and provides semi-automatic layout methods as well as hand layout. It also has several special functions which are not able to find in other layout tools for the module generation, and hence the designer can generate modules very fast. The layout editors implemented in C language with X-win-dow Motif environment. When we compare our editor with the previous layout editor Seadali, the design time is reduced by a factor of two for several benchmark circuits.

• The KIPS Transactions:PartB
• /
• v.13B no.3 s.106
• /
• pp.223-230
• /
• 2006

A window-based image processing is an elementary part of image processing area. Because window-based image processing is computationally intensive and data intensive, it is hard to perform ail of the operations of a window-based image processing in real-time by using a software program on general-purpose computers. This paper proposes a parallel hardware architecture that can perform a window-based image processing in real-time using FPGA(Field Programmable Gate Array). A dynamic threshold circuit and a local histogram equalization circuit of the proposed architecture are designed using VHDL(VHSIC Hardware Description Language) and implemented with an FPGA. The performances of both implementations are measured.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.154-154
• /
• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.7
• /
• pp.513-519
• /
• 2001

We proposed Si-rich tungsten silicide (WSix) films for alternate gate electrode of deep-submicron MOSFETs. The investigation of WSix films deposited directly on SiO$_2$ indicated that the annealing of as-deposited films using a rapid thermal processor (RTP) results in low resitivity, as well as negligible fluorine (F) diffusion. Specifically, the resitivity of RTP-annealed samples at 800 $^{\circ}C$ for 3 minutes in vacuum was ~160 $\mu$$\Omega$ . cm, and the irregular growth of an extra SiO$_2$ layer due to F diffusion during annealing has not been observed. In addition, the analysis of the WSix-SiO$_2$-Si (MOS) capacitors exhibits excellent electrical characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.24 no.3
• /
• pp.182-187
• /
• 2011

In this paper, PBTI characteristics of NMOSFETs with La incorporated HfSiON and HfON are compared in detail. The charge trapping model shows that threshold voltage shift (${\Delta}V_{\mathrm{T}}$) of NMOSFETs with HfLaON is greater than that of HfLaSiON. PBTI lifetime of HfLaSiON is also greater than that of HfLaON by about 2~3 orders of magnitude. Therefore, high charge trapping rate of HfLaON can be explained by higher trap density than HfLaSiON. The different de-trapping behavior under recovery stress can be explained by the stable energy for U-trap model, which is related to trap energy level at zero electric field in high-k dielectric. The trap energy level of two devices at zero electric field, which is extracted using Frenkel-poole emission model, is 1,658 eV for HfLaSiON and 1,730 eV for HfLaON, respectively. Moreover, the optical phonon energy of HfLaON extracted from the thermally activated gate current is greater than that of HfLaSiON.

• Journal of Power Electronics
• /
• v.16 no.1
• /
• pp.362-373
• /
• 2016

The on-line measurement of high-power IGBT collector current is important for the hierarchical control and short-circuit and overcurrent protection of its driver and the sensorless control of the converter. The conventional on-line measurement methods for IGBT collector current are not suitable for engineering measurement due to their large-size, high-cost, low-efficiency sensors, current transformers or dividers, etc. Based on the gate driver, this paper has proposed a current measuring circuit for IGBT collector current. The circuit is used to conduct non-intervention on-line measurement of IGBT collector current by detecting the voltage drop of the IGBT power emitter and the auxiliary emitter terminals. A theoretical analysis verifies the feasibility of this circuit. The circuit adopts an operational amplifier for impedance isolation to prevent the measuring circuit from affecting the dynamic performance of the IGBT. Due to using the scheme for integration first and amplification afterwards, the difficult problem of achieving high accuracy in the transient-state and on-state measurement of the voltage between the terminals of IGBT power emitter and the auxiliary emitter (u_Ee) has been solved. This is impossible for a conventional detector. On this basis, the adoption of a two-stage operational amplifier can better meet the requirements of high bandwidth measurement under the conditions of a small signal with a large gain. Finally, various experiments have been carried out under the conditions of several typical loads (resistance-inductance load, resistance load and inductance load), different IGBT junction temperatures, soft short-circuits and hard short-circuits for the on-line measurement of IGBT collector current. This is aided by the capacitor voltage which is the integration result of the voltage uEe. The results show that the proposed method of measuring IGBT collector current is feasible and effective.

• The Journal of the Acoustical Society of Korea
• /
• v.42 no.6
• /
• pp.544-551
• /
• 2023

Speech enhancement used to improve the perceptual quality and intelligibility of noise speech has been studied as a method using a complex-valued spectrum that can improve both magnitude and phase in a method using a magnitude spectrum. In this paper, a study was conducted on how to apply attention mechanism to complex-valued spectrum-based speech enhancement systems to further improve the intelligibility and quality of noise speech. The attention is performed based on additive attention and allows the attention weight to be calculated in consideration of the complex-valued spectrum. In addition, the global average pooling was used to consider the importance of the feature map. Complex-valued spectrum-based speech enhancement was performed based on the Deep Complex U-Net (DCUNET) model, and additive attention was conducted based on the proposed method in the Attention U-Net model. The results of the experiments on noise speech in a living room environment showed that the proposed method is improved performance over the baseline model according to evaluation metrics such as Source to Distortion Ratio (SDR), Perceptual Evaluation of Speech Quality (PESQ), and Short Time Object Intelligence (STOI), and consistently improved performance across various background noise environments and low Signal-to-Noise Ratio (SNR) conditions. Through this, the proposed speech enhancement system demonstrated its effectiveness in improving the intelligibility and quality of noisy speech.