• 한국재료학회지
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• 제3권6호
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• pp.638-644
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• 1993

티타니움 폴리사이드 MOS(metal oxide semiconducter)캐퍼시타 구조에서 두께가 8nm인 게이트산화막의 절연파괴강도의 열화거동을 열처리조건 및 폴리실리콘막의 두께를 달리하여 조사했다. 티타니움 폴리사이드 게이트에서 게이트산화막의 전연피괴특성은 열처리 온도가 높을수록, 열처리시간이 길수록 많이 열화되어 실리사이드의 하부막인 잔류 폴리실리콘의 두께가 얇을수록 그 정도는 심해진다. 티타니움 실리사이드가 게이트산화막고 직접적인 접촉이 없더라도 게이트산화막의 신회성이 열화되는 것을 알 수 있었다. 실리사이드 형성후 열처리에 따른 게이트 산화막의 절연파괴특성열화는 티타니움 원자가 폴리실리콘을 통해 게이트산화막으로 확산되어 게이트산화막에서 티타니움의 고용량이 증가한 때문인 것이 SIMS분석 결과로부터 확인되었다.

• 대한전자공학회논문지SD
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• 제45권9호
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• pp.21-25
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• 2008

본 연구에서는 MOSFET의 RF 성능을 극대화하기 위해 단위 게이트 finger 폭($W_u$)에 대한 $f_T$ 및 $f_{max}$의 종속데이터를 측정하고 이 결과를 소신호 모델 파라미터들을 추출함으로써 새롭게 분석하였다. 이러한 물리적 분석결과로 $f_T$의 최대값이 존재하는 원인은 좁은 $W_u$에서 $W_u$에 무관한 parasitic gate-bulk capacitance와 넓은 $W_u$에서 트랜스컨덕턴스의 증가율이 감소하는 wide width effect에 의한 것임을 알 수 있다. 또한, $f_{max}$의 최대값은 게이트저항이 좁은 $W_u$에서 크게 줄어들고 넓은 $W_u$에서 점점 일정하게 되는 non-quasi-static effect에 의해 발생된다는 사실이 밝혀졌다.

• 한국항해항만학회지
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• 제31권9호
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• pp.771-778
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• 2007

A container terminal gate is not only an entrance of containers, but also the first input point of containers' information. Therefore, to achieve the accuracy of container information, there are various containers' numbers recognition methods used. Gate productivity can significantly vary depending upon those recognition methods. Recently, RFID which is one of the u-IT businesses run by the Korean government is under consideration for application to the gate as an automatic system. If RFID is used, it is expected to have both the qualitative benefits through avoiding defects of other systems and the quantitative benefits by improving productivity. Hence, this study aims to provide some insight on the benefits of RFID, and to compare productivity of the existing gate system with the RFID gate system based on computer simulation.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2007년도 추계학술대회 및 제23회 정기총회
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• pp.309-310
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• 2007

컨테이너터미널의 Gate는 컨테이너의 출입구를 의미하는 것 외에 컨테이너 정보의 최초 입력점이라는 중요한 의미를 가지고 있다. 따라서 컨테이너 정보의 정확한 습득을 위해 다양한 컨테이너 변호 인식방법이 사용되고 있으며, 이러한 적용방법에 따라 Gate의 생산성에도 많은 차이가 발생하고 있다. 최근, 정부의 u-IT사업추진에 따라 적용되기 시작한 RFID를 이용한 Gate자동화 방식은 기존시스템에 대한 새로운 접근을 요구하게 되었다. RFID를 이용함에 따라 각 시스템의 단점을 보완하는 정성적 이점과 더불어 정량적 생산성 향상이라는 기대치도 높아지게 되었다. 따라서 본 연구에서는 RFID를 이용한 Gate 자동화 시스템과 기존의 Gate시스템과의 생산성 차이를 시뮬레이션을 통해 검증함으로써 RFID 방식의 Gate를 고려하고 있는 컨테이너터미널에 관련된 정보를 제공하고자 하였다.

• 한국정보통신학회논문지
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• 제6권7호
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• pp.1074-1078
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• 2002

본 논문에서는 main gate(MG)와 side gate(SG)를 갖는 double gate(DG) MOSFET를 디자인하고 TCAD를 이용하여 시뮬레이션하였다. MG와 SG의 길이(LMG, LSG)는 각각 50nm, 70nm로 하였으며, MG와 SG의 전압(VMG, VSG)이 각각 1.5V, 3.0V일 때 드레인전압(VD)을 0에서 1.5V까지 변화시키면서 핀치오프특성을 조사하였다. LMG가 아주 작음에도 불구하고, 핀치-오프특성이 아주 좋게 나타났다. 이것은 DG MOSFET의 VMG가 게이트를 제어하는 역할을 잘 수행하여 나노 구조에서 유용한 구조임을 알 수 있었다.

• 건축역사연구
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• 제19권2호
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• pp.117-132
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• 2010

The Great south gate of Seoul Castle, Sung-Rye-Mun, the east gate of Seoul Castle, Hung-In-Ji-Mun, the south gate of Hwa-Sung Castle, Pal-Dal-Mun and the north gate of Hwa-Sung Castle, Jang-An-Mun are typical significant castle gate of Chosun Dynasty. They have a lot in common with exterior. Additionally there are also something common in dimensions. At first, the arch dimensions of lower story is very similar and the columns of upper story are the regular intervals. Purpose of this study is to confirm similarities above mentioned were intended on purpose and if then what was the reason. The results of this study were described separately as follows. 1. The widths of the arches were based on each 16Cheok and 18Cheok. 2. The heights of the arches followed less strictly rule than the widths. 3. The widths of the arches, 16Cheok was same size as width of middle-size road (中路, Jung-Ro) inside the Castle town in Chosun Dynasty. 4. The widths of the arches, 16Cheok was the standard size of exit went through castle and then the standard size of road arrived at one's destination. 5. The widths of the arches had an effect on the intervals between the columns of the upper story. Finally we recognized that in Chos${\u{o}}$n Dynasty the widths of the gate arches in Seoul castle and Hwa-Sung castle had relevance to the city planning largely and widths of the gate arches had an effect on the intervals between the columns of the upper story partly.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 전기전자학회논문지
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• 제7권1호
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• pp.56-62
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• 2003

본 논문에서는 유한체 $GF(2^2)$상에서의 가산기와 승산기를 전류모드인 T-gate를 이용하여 설계하였다. 제시된 회로는 전류 모드에서 동작하는 T-gate의 조합으로 가산 연산과 승산 연산을 수행하는 연산기를 설계하였다. T-gate는 전류 미러와 전송 게이트로 구성되며 4치 T-gate를 설계, 이를 이용하여 $GF(2^2)$의 가산기와 승산기를 1.5um CMOS 공정을 사용하였다. 전원전압은 DC 3.3V이며 단위 전류는 15uA이다. 본 논문에서 제시한 전류 모드 CMOS 연산기는 T-gate의 배열에 의한 모듈성의 이점을 가지고 있으므로 다치 T-gate를 구현하여 다치 연산기를 쉽게 구현할 수 있게 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.463-466
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• 2000

According to the development of the semiconductor micro device technology, IC chip trends the high integrated, low power tendency. Nowadays, it can be showed the tendency of single chip in system level. But in the system level, IC operates by multi power supply voltages. So, semiconductor process is necessary for these multi power operation. Therefore, in this paper, dual gate high voltage device that operate by multi power supply of 5V and 20V fabricated in the 0.5${\mu}{\textrm}{m}$ CMOS process technology and its electrical characteristics were analyzed. The result showed that the characteristics of the 5V device almost met with the SPICE simulation, the SPICE parameters are the same as the single 5V device process. And the characteristics of 20V device showed that gate length 3um device was available without degradation. Its current was 520uA/um, 350uA/um for NMOS, PMOS and the breakdown voltages were 25V, 28V.