• Korean Journal of Materials Research
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• v.3 no.6
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• pp.638-644
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• 1993

The degradation of dielectric breakdown field of 8nm-thick gate oxide ($SiO_2$) for Tipolycide MOS(meta1-oxide-semiconductor) capacitor with different annealing conditions and thickness of the polysilicon film on gate oxide was investigated. The degree of degradation in dielectric breakdown strength of the gate oxide for Ti-polycide gate became more severe with increasing annealing temperature and time, especially, for the case that thickness of the polysilicon film remained on the gate oxide after silicidation was reduced. The gate oxide degradation may be occurred by annealing although there is no direct contact of Ti-silicide with gate oxide. From SIMS analysis, it was confirmed that the degration of gate oxide during annealing was due to the diffusion of titanium atoms into the gate oxide film through polysilicon from the titanium silicide film.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.21-25
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• 2008

In this study, to maximize RF performance of MOSFETs, $f_T$ and $f_{max}$ dependent data on $W_u$ are measured and newly analyzed by extracting small-signal model parameters. From the physical analysis results, it is found that a peak value of $f_T$ is generated by $W_u$-independent parasitic gate-bulk capacitance at narrow $W_u$ and the wide width effect of reducing the increasing rate of transconductance at wide $W_u$. In addition, it is revealed that a maximum value of $f_{max}$ is caused by the non-quasi-static effect that the gate resistance is greatly reduced at narrow $W_u$ and becomes constant at wide $W_u$.

• Journal of Navigation and Port Research
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• v.31 no.9
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• pp.771-778
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• 2007

A container terminal gate is not only an entrance of containers, but also the first input point of containers' information. Therefore, to achieve the accuracy of container information, there are various containers' numbers recognition methods used. Gate productivity can significantly vary depending upon those recognition methods. Recently, RFID which is one of the u-IT businesses run by the Korean government is under consideration for application to the gate as an automatic system. If RFID is used, it is expected to have both the qualitative benefits through avoiding defects of other systems and the quantitative benefits by improving productivity. Hence, this study aims to provide some insight on the benefits of RFID, and to compare productivity of the existing gate system with the RFID gate system based on computer simulation.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2007.12a
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• pp.309-310
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• 2007

컨테이너터미널의 Gate는 컨테이너의 출입구를 의미하는 것 외에 컨테이너 정보의 최초 입력점이라는 중요한 의미를 가지고 있다. 따라서 컨테이너 정보의 정확한 습득을 위해 다양한 컨테이너 변호 인식방법이 사용되고 있으며, 이러한 적용방법에 따라 Gate의 생산성에도 많은 차이가 발생하고 있다. 최근, 정부의 u-IT사업추진에 따라 적용되기 시작한 RFID를 이용한 Gate자동화 방식은 기존시스템에 대한 새로운 접근을 요구하게 되었다. RFID를 이용함에 따라 각 시스템의 단점을 보완하는 정성적 이점과 더불어 정량적 생산성 향상이라는 기대치도 높아지게 되었다. 따라서 본 연구에서는 RFID를 이용한 Gate 자동화 시스템과 기존의 Gate시스템과의 생산성 차이를 시뮬레이션을 통해 검증함으로써 RFID 방식의 Gate를 고려하고 있는 컨테이너터미널에 관련된 정보를 제공하고자 하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1074-1078
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• 2002

In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator U .WOSFET have the main gate length of %m and the side gate length of 70nm. Then, u'e have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nano scale.

• Journal of architectural history
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• v.19 no.2
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• pp.117-132
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• 2010

The Great south gate of Seoul Castle, Sung-Rye-Mun, the east gate of Seoul Castle, Hung-In-Ji-Mun, the south gate of Hwa-Sung Castle, Pal-Dal-Mun and the north gate of Hwa-Sung Castle, Jang-An-Mun are typical significant castle gate of Chosun Dynasty. They have a lot in common with exterior. Additionally there are also something common in dimensions. At first, the arch dimensions of lower story is very similar and the columns of upper story are the regular intervals. Purpose of this study is to confirm similarities above mentioned were intended on purpose and if then what was the reason. The results of this study were described separately as follows. 1. The widths of the arches were based on each 16Cheok and 18Cheok. 2. The heights of the arches followed less strictly rule than the widths. 3. The widths of the arches, 16Cheok was same size as width of middle-size road (中路, Jung-Ro) inside the Castle town in Chosun Dynasty. 4. The widths of the arches, 16Cheok was the standard size of exit went through castle and then the standard size of road arrived at one's destination. 5. The widths of the arches had an effect on the intervals between the columns of the upper story. Finally we recognized that in Chos${\u{o}}$n Dynasty the widths of the gate arches in Seoul castle and Hwa-Sung castle had relevance to the city planning largely and widths of the gate arches had an effect on the intervals between the columns of the upper story partly.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.56-62
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• 2003

In this paper, we designed a adder and a multiplier using current mode T-gate on $GF(2^2)$. The T-gate is consisted of current mirror and pass transistor, the designed 4-valued T-gate used adder and multiplier on $GF(2^2)$. We designed its under 1.5um CMOS standard technology. The unit current of the circuits is 15㎂, and power supply is 3.3V VDD. The proposed current mode CMOS operator have a advantage of module by T-gate`s arrangement, and so we easily implement multi-valued operator.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.463-466
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• 2000

According to the development of the semiconductor micro device technology, IC chip trends the high integrated, low power tendency. Nowadays, it can be showed the tendency of single chip in system level. But in the system level, IC operates by multi power supply voltages. So, semiconductor process is necessary for these multi power operation. Therefore, in this paper, dual gate high voltage device that operate by multi power supply of 5V and 20V fabricated in the 0.5${\mu}{\textrm}{m}$ CMOS process technology and its electrical characteristics were analyzed. The result showed that the characteristics of the 5V device almost met with the SPICE simulation, the SPICE parameters are the same as the single 5V device process. And the characteristics of 20V device showed that gate length 3um device was available without degradation. Its current was 520uA/um, 350uA/um for NMOS, PMOS and the breakdown voltages were 25V, 28V.