• 제목/요약/키워드: Two-switch

검색결과 804건 처리시간 0.024초

X-band Microwave Photonic Filter Using Switch-based Fiber-Optic Delay Lines

  • Jung, Byung-Min
    • Current Optics and Photonics
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    • 제2권1호
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    • pp.34-38
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    • 2018
  • An X-band microwave photonic (MWP) filter using switch-based fiber-optic delay lines has been proposed and experimentally demonstrated. It is composed of two electro-optic modulators (EOMs) and $2{\times}2$ optical MEMS-switch-based fiber-optic delay lines. By changing time-delay difference and coefficients of each wavelength signal by using fiber-optic delay lines and an electro-optic modulator, respectively, a bandpass filter or a notch filter can be implemented. For an X-band MWP filter with four channel elements, fiber-optic delay lines with the unit time-delay of 50 ps have been experimentally realized and the frequency responses corresponding to the time-delays has been measured. The measured frequency response error at center frequency and the time-delay difference error were 180 MHz at 10 GHz and 3.2 ps, respectively, when the fiber-optic delay line has the time-delay difference of 50 ps.

Linked-list 구조를 갖는 ATM용 공통 버퍼형 메모리 스위치 설계 (Design of a shared buffer memory switch with a linked-list architecture for ATM applications)

  • 이명희;조경록
    • 한국통신학회논문지
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    • 제21권11호
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    • pp.2850-2861
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    • 1996
  • This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

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버퍼를 장착한 a$\times$b 스위치로 구성된 Fat-tree 망의 성능분석 (Analytical modeling of a Fat-tree Network with buffered a$\times$b switches)

  • 신태지;양명국
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 I
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    • pp.374-377
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    • 2003
  • In this paper, a performance evaluation model of the Fat-Tree network with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem in the switch network The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on the various sizes of Fat-tree networks that use the multiple a$\times$b buffered crossbar switches. It is observed that both analysis and simulation results are match closely.

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멀티캐스트 환경에서 향상된 처리율을 갖는 공유 다중 버퍼 ATM스위치의 VLSI 설계 (VLSI design of a shared multibuffer ATM Switch for throughput enhancement in multicast environments)

  • Lee, Jong-Ick;Lee, Moon-Key
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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    • pp.383-386
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    • 2001
  • This paper presents a novel multicast architecture for shared multibuffer ATM switch, which is tailored for throughput enhancement in multicast environments. The address queues for multicast cells are separated from those for unicast cells to arbitrate multicast cells independently from unicast cells. Three read cycles are carried out during each cell slot and multicast cells have chances to be read from shared buffer memory(SBM) in the third read cycle provided that the shared memory is not accessed to read a unicast cell. In this architecture, maximum two cells are queued at each fabric output port per time slot and output mask choose only one cell. Extensive simulations are carried out and it shows that the proposed architecture has enhanced throughput comparing with other multicast schemes in shared multibuffer switch architecture.

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교번 스위치를 활용한 시공간 및 주파수공간 블록 코딩의 하이브리드 알고리즘 (Hybrid Algorithm of Space Time and Space Frequency Block Coding Technique using Alternate Time Switch)

  • 정혁구
    • 전기학회논문지P
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    • 제66권1호
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    • pp.48-52
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    • 2017
  • This paper proposes a hybrid algorithm of space-time block coding and space-frequency block coding using alternate time switch. The traditional alternate time-switched space-time or space-frequency block coding technique for orthogonal frequency division multiplexing system does not provide a good performance with a variety of communication environments. This hybrid algorithm has searched good performance ranges in various environments in view points of mobile speed and doppler frequency. In this paper, we investigate better performance ranges for two algorithms, suggest a hybrid algorithm for dynamically changing communication environments, propose a structure for transmitter and receiver, and show that its performance is better than the traditional algorithm by simulations.

태양광 멀티레벨 단상 인버터를 위한 단일 스위치를 가지는 삼중 출력 DC/DC 컨버터 설계 및 해석 (Design and Analysis of a Triple Output DC/DC Converter with One Switch for Photovoltaic Multilevel Single Phase Inverter)

  • 최우석;박성준
    • 조명전기설비학회논문지
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    • 제28권8호
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    • pp.82-89
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    • 2014
  • The industrial products to use single phase inverter are raised the necessity of power quality improvement, such as AC Motor Driver, Lighting, Renewable energy power converter. Also, it is increasing that applied the single phase multilevel inverter for high quality power at renewable energy power converter. Especially, the photovoltaic multilevel inverters have at least more than two DC_Link and more than one DC/DC Converter. This paper proposes a triple output DC/DC Converter with one switch for photovoltaic multilevel inverter. The proposed converter has advantages of low cost and volume because it has one switch. The operation principle of the converter is analyzed and verified. A prototype is implemented to verify of the proposed converter.

단상유도전동기의 입력단 직렬 인덕터를 이용한 전류검출 (The Current Detect of Single Phase Induction Motor Using Series Inductor)

  • 서강성;박수강;박제웅;김대곤;조금배;백형래
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2002년도 전력전자학술대회 논문집
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    • pp.205-208
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    • 2002
  • The single phase induction motor(SPIM) with two windings, main and auxiliary winding, is widely used due to ruggedness, low maintenance and simplicity of construction. There are several ways of starting single phase induction motor. The most common method is to use centrifugal switch that is connected in series with a capacitor. But the centrifugal switch that is the external starting system has many problems. In this paper, we use triac to overcome defects that happen by centrifugal switch, Also we used inductor that connected with main winding to get a gate trigger voltage signal. Experiments are focused on a capacitor starling single phase induction motor.

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WRspice를 이용한 D2 cell의 simulation 연구 (Study of D2 cell simulation by using WRspice)

  • 남두우;강준희
    • 한국초전도저온공학회:학술대회논문집
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    • 한국초전도저온공학회 2003년도 학술대회 논문집
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    • pp.92-94
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    • 2003
  • In superconductive digital logic circuits, D2 cells can be used to compose a decoder an important component of an Arithmetic Logic Unit (ALU). In this wor, we simulated D2 cell by using WRspice. D2 cell has one input, one switch input, and two outputs (output1 and output2). D2 cell functions in such way that output1 follows the input and output2 is the complement of the input data, when the switch input is "0, ". However, when there is a switch input "1, " the opposite output signals are generated. In this paper, we optimized a D2 cell by using WRspice, and obtained the minimum margin of 26%. Our optimized D2 cell will play a key role in the ALU fabrication.the ALU fabrication.

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Switching properties of bivariate Shewhart control charts for monitoring the covariance matrix

  • Gwon, Hyeon Jin;Cho, Gyo-Young
    • Journal of the Korean Data and Information Science Society
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    • 제26권6호
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    • pp.1593-1600
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    • 2015
  • A control chart is very useful in monitoring various production process. There are many situations in which the simultaneous control of two or more related quality variables is necessary. We construct bivariate Shewhart control charts based on the trace of the product of the estimated variance-covariance matrix and the inverse of the in-control matrix and investigate the properties of bivariate Shewart control charts with VSI procedure for monitoring covariance matrix in term of ATS (Average time to signal) and ANSW (Average number of switch) and probability of switch, ASI (Average sampling interval). Numerical results show that ATS is smaller than ARL. From examining the properties of switching in changing covariances and variances in ${\Sigma}$, ANSW values show that it does not switch frequently and does not matter to use VSI procedure.

PSPICE Modeling of Commercial ICs for Switch-Mode Power Supply (SMPS) Design and Simulation

  • Yi, Yun-Jae;Yu, Yun-Seop
    • Journal of information and communication convergence engineering
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    • 제9권1호
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    • pp.74-77
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    • 2011
  • PSPICE modeling of a commercial LED driver IC (TOP245P) and PC817A optocoupler is proposed for the switch-mode power supply (SMPS) (applicable to LED driver) design and simulation. An analog behavioral model of the TOP245P IC including the shunt regulator, under-voltage(UV) detection, over-voltage(OV) shut-down and SR flip-flop is developed by using PSPICE. The empirical equation of PC817A current transfer ratio (CTR) is fitted from the datasheet of PC817A. Two types of SMPSs are simulated with the averaged-model and switching-model. The simulation results by the proposed PSPICE models are in good agreement with those in the data sheet and an experimental data.