• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.599-602
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• 2002

A novel rapid prototyping (RP) process, an automated transfer type variable lamination manufacturing process (Automated VLM-ST) has been developed. In Automated VLM-ST, a vacuum chuck and linear moving system transfer the plate type material with two pilot holes to the rotation stage. A four-axis synchronized hotwire cutter cuts the material twice to generate Automated Unit Shape Layer (AUSL) with the desired width, side slopes, length, and two reference shapes in accordance with CAD data. Each AUSL is stacked on the stacking plate with two pilot pins using the pilot holes in AUSL and the pilot pins. Subsequently, adhesive is supplied to the top surface of the stacked AUSL by a bonding roller and pressure is simultaneously applied to the bottom surface of the stacked AUSL. Finally, three-dimensional shapes are rapidly fabricated. This paper describes the procedure for generating the cutting path data (AUSL data) f3r automated VLM-ST. The method for the generation of the Automated Unit Shape Layer (AUSL) in Automated VLM-ST was practically applied and fabricated for a various shapes.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.2
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• pp.632-657
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• 2022

Detecting web attacks is a major challenge, and it is observed that the use of simple models leads to low sensitivity or high false positive problems. In this study, we aim to develop a robust two-stage deep learning based stacked ensemble web application firewall. Normal and abnormal classification is carried out in the first stage of the proposed WAF model. The classification process of the types of abnormal traffics is postponed to the second stage and carried out using an integrated stacked ensemble model. By this way, clients' requests can be served without time delay, and attack types can be detected with high sensitivity. In addition to the high accuracy of the proposed model, by using the statistical similarity and diversity analyses in the study, high generalization for the ensemble model is achieved. Within the study, a comprehensive, up-to-date, and robust multi-class web anomaly dataset named GAZI-HTTP is created in accordance with the real-world situations. The performance of the proposed WAF model is compared to state-of-the-art deep learning models and previous studies using the benchmark dataset. The proposed two-stage model achieved multi-class detection rates of 97.43% and 94.77% for GAZI-HTTP and ECML-PKDD, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.11-17
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• 2004

In this paper, A miniature broad-band dime antenna is designed. This antenna consists of two stacked circular patches that create two cylindrical slots resonating at two slightly different frequencies, fed by a strategically positioned coaxial prove. To increase the bandwidth of microstrip patch antenna, a configuration of stacked type is used. Furthermore, to reduce the size of microstrip patch antenna and obtain a double resonant behavior, two shorting-walls are used. Experimental results show that the antenna bandwidth is about 26% centered at 5.8㎓ and are close agreement with the calculation results by HFSS 7.0 software.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1546-1548
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• 2002

In this paper, the electrical characteristics of pentacene thin film transistors(TFTs) with stacked and surface-treated gate insulators have been investigated. The semiconductor layer of pentacene was thermally evaporated onto the stacked gate insulators. For the gate insulating materials. PVP(PolyvinylPhenol) and polystyrene were spin-coated with two different stacking orders, PVP-polystyrene and polystyrene-PVP. Rapid solvent evaporation during the spin-coating processes of these insulating layers produces non-equilibrium phase morphologies accompanied by surface undulations on gate insulator interfaces. This non-equilibrium phase morphology affects the growth mode of the subsequent pentacene layer. Therefore, in order to smoothen the gate dielectric surfaces, gate dielectric surfaces were rubbed laterally along the direction from the drain to the source TFTs with with stacked and surface-treated gate insulators have provided improved operational characteristics.

• Journal of the Korea Society of Computer and Information
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• v.27 no.1
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• pp.33-41
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• 2022

This paper describes a planar microstrip patch antenna designed on dielectric substrate. Two types of planar microstrip patch antennas are studied for the 5G wireless applications, one type is conventional microstrip structure, the other type is stacked microstrip structure fed by coaxial probe. Using electromagnetically coupling method, stacked microstrip patch antenna employing a multi-layer substrate structure was designed. The results indicate that the proposed stacked microstrip patch antenna performs well at 5G wireless service bandwith a broadband from 3.42GHz to 3.70GHz. The impedance bandwidth(VSWR≤2) is 360MHz(10.28%) from 3.42GHz to 3.78GHz. In this paper, through the designing of a stacked microstrip patch antenna, we have presented the availability for 5G wireless repeater system.

• Progress in Superconductivity
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• v.5 no.1
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• pp.9-12
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• 2003

We observed the splitting of the fluxon-flow branches in the current-voltage characteristics of serially stacked intrinsic Josephson junctions (IJJs) formed in $Bi_2$$Sr_2$$CaCu_2$$O_{ 8＋x}$ single crystals in the long-junction limit. Stacks of IJJs were sandwiched between two Au electrodes deposited on the top and the bottom of the stack using the ‘double-side cleaving technique’. In all the samples studied, the branch splitting started occurring for a dense fluxon configuration around 2 T and became more distinct in a higher magnetic field range. This observation can be explained in terms of switching between different Josephson fluxon modes in resonance with the collective plasma oscillations induced by both inductive and capacitive coupling between stacked IJJs. This is the first detailed and quantitative identification of the coherent flux-flow modes in stacked..

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2231-2232
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• 2006

Multi-stacked HTS tapes are needed to conduct large current in the power application of superconducting machine. This paper deals with the transport current loss of multi-stacked YBCO coated conductor. YBCO coated conductor that was used in this experiment has two Cu layers above and below of YBCO layer for stabilization. Transport losses of four different stacks, single, 2 stack, 3 stack and 4 stack, were measured. Measured results were compared analytic equation suggested by Norris.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.418-422
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• 2003

In this paper a dual-band circularly polarized stacked microstrip antenna for Global Positioning System (GPS) service and Digital Multimedia Broadcasting (DMB) service is designed. By stacking two different corner-truncated square microstrip patches, dual-band, dual polarization characteristic is obtained. Experimental results show impedance bandwidth of 60 MHz (3.8%) and axial ratio bandwidth of 6 MHz (0.4%) in GPS and impedance bandwidth of 126 MHz (4.7%) and axial ratio bandwidth of 30MHz (1.1%) in DMB.

• Korean Journal of Materials Research
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• v.17 no.7
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1265-1266
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• 2006

Multi-stacked HTS tapes are needed to conduct large current in the power application of superconducting machine. This paper deals with the transport current loss of multi-stacked YBCO coated conductor. YBCO coated conductor that was used in this experiment has two Cu layers above and below of YBCO layer for stabilization. Transport losses of four different stacks, single, 2 stack, 3 stack and 4 stack, were measured. Measured results were compared analytic equation suggested by Norris.