• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.277-280
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• 2000

In this paper, we designed a turbo decoder using VHDL. To maximize effective free distance of the turbo code, we implemented pseudo random interleaver. A MAP(Maximum a posteriori) decoder is used as a primimary decoder. We avoided multiplication by using lookup tables(ROM). We expect that this small-sized turbo decoder is suitable for mobile communication. We simulated turbo decoder with Altera MAX+PLUS II.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 D
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• pp.3148-3150
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• 2000

Turbo codes that have attracted a great attention in recent years are applied to wireless communication networks that require variable quality of service and transmit over unknown fading channel. A MAP decoder is the constituent of turbo decoder. In this paper, we propose a high speed architecture of MAP decoder and a new normalization technique, In conclusion, this paper presents the efficient implementation of serial block MAP decoder for turbo codes.

• 한국군사과학기술학회지
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• 제3권1호
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• pp.116-126
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• 2000

Turbo codes are the most exciting and potentially important development in coding theory in recent years. They were introduced in 1993 by Berrou, Glavieux and $Thitimajshima,({(1)}$ and claimed to achieve near Shannon-limit error correction performance with relatively simple component codes and large interleavers. A required Eb/N0 of 0.7㏈ was reported for BER of $10^{-5}$ and code rate of $l/2.^{(1)}$ However, to implement the turbo code system, there are various important details that are necessary to reproduce these results such as AGC gain control, optimal wordlength determination, and metric rescaling. Further, the memory required to implement MAP-based turbo decoder is relatively considerable. In this paper, we confirmed the accuracy of these claims by computer simulation considering these points, and presented a optimal wordlength for Turbo code design. First, based on the analysis and simulation of the turbo decoder, we determined an optimal wordlength of Turbo decoder. Second, we suggested the MAP decoding algorithm based on sliding-window method which reduces the system memory significantly. By computer simulation, we could demonstrate that the suggested fixed-point Turbo decoder operates well with negligible performance loss.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.425-428
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• 1999

Turbo decoder were shown to achieve performance within 0.7㏈ of the Shannon capacity limit. This constituted a significant gain in power efficiency over other coding techniques known at the time. In this paper, Turbo code with constraint length K＝4, code rate 1/3, frame size 196bits(6 tail bits), 20㎳ frame and 6bit MAP decoder is implemented using VHDL. The designed Turbo code is used for voice service. Interactions of the system are used to attain large performance improvements.

• 전자공학회논문지
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• 제50권11호
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• pp.50-57
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• 2013

본 논문은 하나 이상의 다양한 길이의 패킷을 동시에 복호할 수 있는 고 처리율 병렬 터보 복호기의 설계를 보인다. 터보 복호기의 병렬 구조는 반복 복호로 인한 긴 디코딩 시간을 절감시키며, 입/출력의 이중 버퍼 구조 설계는 패킷들의 연속적인 복호를 가능하게 함으로써 복호기의 처리율을 향상시킨다. 병렬 터보 복호기는 가장 긴 길이의 패킷을 복호할 수 있도록 설계되기 때문에, 이보다 짧은 길이의 패킷의 복호 시에는 사용하지 않는 PE(Processing Element)가 존재한다. 본 논문의 아이디어는 이 유휴 PE들을 연속적으로 이어지는 다음 패킷의 복호에 즉시 이용함으로써, 복호기 내의 PE 사용 효율을 높이고 처리율을 향상시키는 데 있다. 이를 위하여 여러 패킷의 복호를 동시에 가능하게 하는 제어가 필요하며, 본 논문에서는 이러한 제어 방법을 기술한다. 제안한 방법을 적용하여, 32개의 PE를 사용하면서 최대 6144비트 길이의 패킷을 복호 할 수 있는 병렬 터보 복호기를 구현하였으며, 기존 터보 복호기와 비교하여 약 16% 의 면적 증가가 있었으나, 짧은 패킷의 경우 기존 복호기에 비해 최대 28배의 높은 처리율 향상 효과를 보였다.

• 한국통신학회논문지
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• 제32권4C호
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• pp.379-388
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• 2007

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.

• 한국통신학회논문지
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• 제28권3C호
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• pp.215-223
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• 2003

차세대 이동 통신인 IMT2000에서는 3GPP 및 3GPP2규격 모두에서 터보코드가 채널 코딩기법으로서 길쌈부호와 함께 표준으로 채택되어 있으며 특히 3GPP규격에서는 제한길이 4인 1/3 터보코드가 채택되어 있다. 본 논문에서는 상기 터보 코드를 복호하기 위한 복호기의 구조를 제시하고, 3GPP 규격의 터보 코드를 복호할 수 있는 복호기를 설계하였다. 특히 효율적인 동작을 위하여 내부 SISO 복호기로서 레지스터교환방식을 적용하고 새로운 구조의 누적 메트릭 정규화 부를 포함한 SOVA복호기를 설계하였다. 개발 터보 복호기의 성능 예측을 위하여 MATLAB을 통하여 시뮬레이션하였으며, VHDL을 사용하여 파 모듈의 제어를 위한 제어블럭, 입력 제어 버퍼, SOVA 내부 복호기를 포함한 전체 터보 복호기를 설계하였다. 설계한 복호기는 Synopsys사의 FPGA express에서 합성하고, EPF200SRC240-3 FPGA에 이식하여 하드웨어적으로 동작을 검증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.297-300
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• 2001

Turbo code shows the great performance near Shannon limit on AWGN channel. Mainly, turbo code has been studied and designed for wireless digital communications. There are recent studies that applies turbo decoder on magnetic recording. Because of the limited capacity of magnetic storages, high rate turbo code is used for magnetic storages. This paper presents some issues on implementing high rate turbo code and structures for designing turbo decoder

• Journal of Communications and Networks
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• 제6권3호
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• pp.203-208
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• 2004

A combined precoding and turbo decoding strategy for multi-path frequency-selective fading channels is presented. The precoder and multi-path fading channel are jointly modeled as a finite-state probabilistic channel to provide the multi-stage turbo decoder with its statistics information. Both a priori and a posteriori probabilities are used in the metric computation to improve the system performance. Structures of the combined turbo-encoder, interleaver, and precoder in the transmitter and two-stage turbo decoder in the receiver are described. Performance of the proposed scheme in fixed, Rician and Rayleigh multi-path fading channels are evaluated by simulation. The results indicate that the combined precoding and two-stage turbo decoding strategy provides a considerable performance improvement while maintaining the same inner structure of a conventional turbo decoder.

• Journal of electromagnetic engineering and science
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• 제6권3호
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.