• Transactions on Electrical and Electronic Materials
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• v.15 no.5
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• pp.245-248
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• 2014

$Pt/Al_2O_3/Si_3N_4/SiO_2/Si$ charge trap flash memory structures with various thicknesses of the $Si_3N_4$ charge trapping layer were fabricated. According to the calculated and measured results, we depicted electron loss in a schematic diagram that illustrates how the trap to band tunneling and thermal excitation affects electrons loss behavior with the change of $Si_3N_4$ thickness, temperature and trap energy levels. As a result, we deduce that $Si_3N_4$ thicknesses of more than 6 or less than 4.3 nm give no contribution to improving memory performance.

• Journal of Information Display
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• v.2 no.3
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• pp.60-65
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• 2001

Lateral type poly-silicon field emitters were fabricated by utilizing the LOCOS (Local Oxidation of Silicon) process. For the implementation 'of an ideal field emission device with quasi-zero tunneling barrier, a new and fundamental approach has used conducted by introducing an intelligent carbon-based thin layer on the cathode tip surface via a field-assisted self-aligning of carbon (FASAC) process. Fundamental lowering of the turn-on field for the electron emission was feasible through the control of both the tip shape and surface barrier height.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.12
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• pp.2265-2269
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• 2011

1 kV high-voltage GaN Schottky diode is realized using GaN-on-Si template by oxidizing Ni-Schottky contact. The Auger electron spectroscopy (AES) analysis revealed the formation of $NiO_x$ at the top of Schottky contact. The Schottky contact was changed to from Ni/Au to Ni/Ni-Au alloy/Au/$NiO_x$ by oxidation. Ni diffusion into AlGaN improves the Schottky interface and the trap-assisted tunneling current. In addition, the reverse leakage current and the isolation-leakage current are efficiently suppressed by oxidation. The isolation-leakage current was reduced about 3 orders of magnitudes. The reverse leakage current was also decreased from 2.44 A/$cm^2$ to 8.90 mA/$cm^2$ under -100 V-biased condition. The formed group-III oxides ($AlO_x$ and $GaO_x$) during the oxidation is thought to suppress the surface leakage current by passivating surface dangling bonds, N-vacancies and process damages.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.230-230
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• 2012

Graphene have showed promising performance as electrodes of organic devices such as organic transistors, light-emitting diodes, and photovoltaic solar cells. In particular, among various organic materials of graphene-based organic devices, pentacene has been regarded as one of the promising organic material because of its high mobility, chemical stability. In the bottom-contact device configuration generally used as graphene based pentacene devices, the morphology of the organic semiconductors at the interface between a channel and electrode is crucial to efficient charge transport from the electrode to the channel. For the high quality morphology, understanding of initial stages of pentacene growth is essential. In this study, we investigate self-assembly of pentacene molecules on graphene formed on a 6H-SiC (0001) substrate by scanning tunneling microscopy. At sub-monolayer coverage, adsorption of pentacene molecules on epitaxial graphene is affected by $6{\times}6$ pattern originates from the underlying buffer layer. And the orientation of pentacene in the ordered structure is aligned with the zigzag direction of the edge structure of single layer graphene. As coverage increased, intermolecular interactions become stronger than molecule-substrate interaction. As a result, herringbone structures the consequence of higher intermolecular interaction are observed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.103-110
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• 2001

Gate oxide scaling for sub-l00nm CMOS devices has been studied. Issues on the gate oxide scaling are reviewed, which are boron penetration, reliability, and direct tunneling leakage currents. Reliability of Sub-2.0nm oxides and the device performance degradation due to boron penetration are investigated. Especially, the effect of gate leakage currents on the transistor characteristics is studied. As a result, it is proposed that thinner oxides than previous expectations may be usable as scaling proceeds. Based on the gate oxide thickness optimization process we have established, high performance CMOS transistors of $L_{gate}=70nm$ and $T_{ox}=1.4nm$ were fabricated, which showed excellent current drives of $860\mu\textrm{A}/\mu\textrm{m}$ (NMOS) and $350\mu\textrm{A}/\mu\textrm{m}$ (PMOS) at $I_{off}=10\mu\textrm{A}/\mu\textrm{m}$ and $V_dd=1.2V$, and CV/I of 1.60ps (NMOS) and 3.32ps(PMOS).

• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.4
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• pp.12-18
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• 2002

Silicon on insulator(SOI) wafer is used in a variety of microsensor applications in which thermal deformations and other mechanical effects may dominate device Performance. One of major Problems associated with the manufacturing Processes of the microaccelerometer based on the tunneling current concept is thermal deformations and thermal stresses. This paper deals with finite element analysis(FEA) of residual thermal deformations causing popping up, which are induced in micrormaching processes of a microaccelerometer. The reason for this Popping up phenomenon in manufacturing processes of microaccelerometer may be the bending of the whole wafer or it may come from the way the underetching occurs. We want to seek after the real cause of this popping up phenomenon and diminish this by changing manufacturing processes of mic개accelerometer. In microaccelerometer manufacturing process, this paper intend to find thermal deformation change of the temperature distribution by tunnel gap and additional beams. The thermal behaviors analysis intend to use ANSYS V5.5.3.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.145-150
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• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1232-1236
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• 2003

In this work, we fabricated a gas-sensing device based on porous silicon(PS), and its C-V properties were investigated for sensing alcohol vapor. The structure of the sensor consists of thin Au/oxidized PS/PS/P-Si/Al, where the p-Si is etched anisotropically to be prepared into a membrane-shape. We used alcohol gases vaporized from different alcohol (or ethanol) solutions mixed with pure water at 36$^{\circ}C$, similarly with an alcohol breath measurement to check drunk driving. As the result, I-V curves showed typical tunneling property, and C-V curves were shaped like those of a MIS (metal-insulator-semiconductor) capacitor, where the capacitance in accumulation was increased with alcohol vapor concentration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.175-177
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• 2002

Electrical characteristics of the Si-O superlattice diode as a function of annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy (MBE) system. Consequently, the experimental results of superlattice diode with multilayer Si-O structure showed the stable and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic and quantum device as well as for the replacement of silicon-on-insulator (SOI) in ultra high speed and lower power CMOS devices in the future, and it can be readily integrated with silicon ULSI processing.