• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.26-31
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• 2002

To realize a high integrated Flash memory utilizing SONOS memory devices, the NOR type 1TC(one Transistor Cell) SONOS Flash arrays are fabricated and characterized. This SONOS Flash arrays with common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cell is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$. To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and Bit line erase method are selected as the write operation and the erase method, respectively. The disturbance characteristics according to the write/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• Journal of Magnetics
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• 제14권4호
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• pp.172-174
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• 2009

Nanolithography by atomic force microscope local oxidation was applied to the fabrication of planar-type Ni/Ni oxide/Ni junctions from 10 nm-thick Ni films. The junction characteristics were sensitive to the lithography conditions such as the bias voltage. Successful oxidation produced junctions of nonlinear current-voltage characteristics, implying the formation of oxide barriers. Magnetoresistance (MR) at low temperatures resembled that of spin valves.

• 한국전기전자재료학회논문지
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• 제16권5호
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• pp.372-377
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• 2003

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2003년도 somma/kms meeting
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• pp.98-98
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• 2003

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 춘계학술대회
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• pp.171-172
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• 2018

Dual gate L-shaped tunnel field-effect-transistor (DG-LTFET) is presented in this study. DG-LTFET achieves near vertical subthreshold slope (SS) and its ON current is also found to be higher then both conventional TFET and LTFET. This device could serve as a potential replacement for conventional complimentary metal-oxide-semiconductor (CMOS) technology.

• 한국자기학회지
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• 제10권4호
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• pp.159-163
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• 2000

절연층으로 CoO를 사용한 스핀의존성 터널링 접합 NiFe(30 nm)/CoO(t)/Co(30 nm-t)에서 터널링 자기저항성질을 연구하였다. 3-gun 스퍼터링 시스템에서 4$^{\circ}$tilt-cut (111)Si을 기판으로, 상부자성층으로 Ni$_{80}$Fe$_{20}$를 사용하였고 Co를 하부 자성층으로 사용하였다. 절연층으로 사용된 CoO른 하부 자성층 Co를 산소 플라즈마 산화법과 상온에서의 자연산화를 통해 얻었다. CoO를 플라즈마 산화법으로 얻은 경우 플라즈마 산화시간이 증가할수록 자기이력곡선에서 반강자성 물질인 CoO에 의해 NiFe와 Co의 보자력이 증가하는 것을 관찰할 수 있었다. 플라즈마 산화된 CoO의 경우, 상온에서 1mA의 감지전류를 흘려줬을 경우 최대 1.2 %의 자기저항비를 얻을 수 있었다. 자연산화법으로 CoO를 얻은 경우 감지 전류 1 mA에서 4.8 %의 자기저항비를 관찰할수 있었고, 감지전류 1.5 mA의 경우 28 %의 자기저항비와 10.9 ㏀$\times$$\mu\textrm{m}$$^2$의 값을 얻을 수 있었다. 저항$\times$면적값이 2.28 ㏀$\times$$\mu\textrm{m}$$^2$일 때 최대 120 %의 자기저항비를 얻을 수 있었다.다.

• Progress in Superconductivity
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• 제12권2호
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• pp.114-117
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• 2011

We report our efforts on the development of Nb-based non-hysteretic Josephson junction fabrication process for quantu device applications. By adopting and modifying the existing Nb-aluminum oxide tunnel junction process, we develop a process for non-hysteretic Josephson junction circuits using metal-silicide as metallic barrier material. We use sputter deposition of Nb and $MoSi_2$, PECVD deposition of silicon oxide as insulator material, and ICP-RIE for metal and oxide etch. The advantage of the metal-silicide barrier in the Nb junction process is that it can be etched in $SF_6$ RIE together with Nb electrode. In order to define a junction area precisely and uniformly, end-point detection for the RIE process is critical. In this paper, we employed thin Al layer for the etch stop, and optimized the etch condition. We have successfully demonstrated that the etch stop properties of the inserted Al layer give a uniform etch profile and a precise thickness control of the base electrode in Nb trilayer junctions.

• 한국재료학회지
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• 제30권2호
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• pp.99-104
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• 2020

Recent discoveries of ferroelectric properties in ultrathin doped hafnium oxide (HfO₂) have led to the expectation that HfO₂ could overcome the shortcomings of perovskite materials and be applied to electron devices such as Fe-Random access memory (RAM), ferroelectric tunnel junction (FTJ) and negative capacitance field effect transistor (NC-FET) device. As research on hafnium oxide ferroelectrics accelerates, several models to analyze the polarization switching characteristics of hafnium oxide ferroelectrics have been proposed from the domain or energy point of view. However, there is still a lack of in-depth consideration of models that can fully express the polarization switching properties of ferroelectrics. In this paper, a Zr-doped HfO₂ thin film based metal-ferroelectric-metal (MFM) capacitor was implemented and the polarization switching dynamics, along with the ferroelectric characteristics, of the device were analyzed. In addition, a study was conducted to propose an applicable model of HfO₂-based MFM capacitors by applying various ferroelectric switching characteristics models.

• 한국재료학회지
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• 제13권4호
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• pp.233-238
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• 2003

Ferromagnetic tunnel junctions, Ta/Cu/Ta/NiFe/Cu/$Mn_{75}$ $Ir_{25}$ $Co_{70}$ $Fe_{30}$/Al-oxide, were fabricated by do magnetron sputtering and plasma oxidation process. The effect of annealing temperature on the local transport properties of the ferromagnetic tunnel junctions was studied using contact-mode Atomic Force Microscopy (AFM). The current images reflected the distribution of the barrier height determined by local I-V analysis. The contrast of the current image became more homogeneous and smooth after annealing at $280^{\circ}C$. And the average barrier height $\phi_{ave}$ increased and its standard deviation $\sigma_{\phi}$ X decreased. For the cases of the annealing temperature more than $300^{\circ}C$, the contrast of the current image became large again. And the average barrier height $\phi_{ave}$ decreased and its standard deviation $\sigma_{\phi}$ increased. Also, the current histogram had a long tail in the high current region and became asymmetric. This result means the generation of the leakage current that is resulted from the local generation of a low barrier height region. In order to obtain the high tunnel magnetoresistance(TMR) ratio, the increase of the average barrier height and the decrease of the barrier height fluctuation must be strictly controlled.led.

• 한국정보통신학회논문지
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• 제7권2호
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• pp.269-275
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• 2003

저전압 프로그래밍이 가능한 플래시메모리를 실현하기 위하여 0.35$\mu\textrm{m}$ CMOS 공정 기술을 이용하여 터널링산화막, 질화막 그리고 블로킹산화막의 두께가 각각 2.4nm, 4.0nm, 2.5nm인 SONOS 트랜지스터를 제작하였으며, SONOS 메모리 셀의 면적은 1.32$\mu$$m^2$이었다. 질화막의 두께를 스케일링한 결과, 10V의 동작 전압에서 소거상태로부터 프로그램상태로, 반대로 프로그램상태에서 소거상태로 스위칭 하는데 50ms의 시간이 필요하였으며, 최대 메모리윈도우는 1.76V이었다. 그리고 질화막의 두께를 스케일링함에도 불구하고 10년 후에도 0.5V의 메모리 윈도우를 유지하였으며, 105회 이상의 프로그램/소거 반복동작이 가능함을 확인하였다. 마지막으로 부유게이트 소자에서 심각하게 발생하고있는 과도소거현상이 SONOS 소자에서는 나타나지 않았다.