• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.211-211
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• 2010

지난 수년간 비휘발성 메모리는 휴대용 전자기기 시장의 증가로 인해 많은 주목을 받아왔다. 그러나 현재 주로 쓰이고 있는 다결정 실리콘을 부유게이트층을 이용한 소자는 한계점을 보이고 있다. 이러한 이유로 최근에는 반도체 나노점이나 금속 나노점을 이용하는 비휘발성 메모리가 각광을 받고 있다. 이 메모리들은 빠른 쓰기/지우기 속도, 긴 저장시간, 낮은 구동전압 등의 이점을 지니고 있다. 본 연구에서는 이온빔 스퍼터링 방법을 이용해 $SiO_2$/Zr nanodots (ND)/$SiO_2$ trilayer 구조를 제작하였다. tunnel oxide와 control oxide의 두께는 각각 3nm, 15nm 이며 Zr의 양을 변화시키며 그에 따른 Zr ND과 메모리 효과의 변화를 관찰하였다. 고분해능 전자현미경과 광전자 분광기를 이용해 Zr ND의 형성을 확인하였고 열처리 후 $ZrO_2$ ND로 상이 변화함을 관찰하였다. -10 ~ +10V의 측정 조건 하에서 Zr의 양이 증가함에 따라 메모리 폭은 최대 5.8V까지 증가하였다. 또한 쓰기 상태에서 메모리 폭과 전하 손실비율은 열처리 후가 감소하였고 이는 $SiO_2$와 Zr ND의 계면에서 생성되는 $ZrO_2$의 영향인 것으로 생각된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.240-240
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• 2010

A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (${\sim}\;1.2{\times}10^{13}/cm^2$) was fabricated. Its structural effect for multiple layers was evaluated and compared to one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with 2-4 multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler-Nordheim (FN)-tunneling could be a candidate structure for future flash memory.

• Vacuum Magazine
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• v.3 no.3
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.67-68
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• 2006

Floating gate non-volatile memory devices with Au nano-particles embedded in SiON or $SiO_2$ dielectrics were fabricated by digital sputtering method. The size and the density of Au are 4nm and $2{\times}10^{-12}cm^{-2}$, respectively. The floating gate memory of MOSFET with 5nm tunnel oxide and 45nm control oxide have been fabricated. This devices revealed a memory effect which due to proGrainming and erasing works perform by a gate bias stress repeatedly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.21-26
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• 2008

We fabricated nano-particles of ZnO, $In_2O_3$ and $SnO_2$ by using the chemical reaction between metal thin films and polyamic acid. The average size and density of these ZnO, $In_2O_3$ and $SnO_2$ nano-particles was approximately 10, 7, and 15 nm, and $2{\times}10^{11},\;6{\times}10^{11},\;2.4{\times}10^{11}cm^{-2}$, respectively. Then, we fabricated nano-floating gate memory (NFGM) devices with ZnO and $In_2O_3$ nano-particles embedded in the devices' polyimide dielectrics and silicon dioxide layers as control and tunnel oxides, respectively. We measured the current-voltage characteristics, endurance properties and retention times of the memory devices using a semiconductor parameter analyzer. In the $In_2O_3$ NFGM, the threshold voltage shift (${\Delta}V_T$) was approximately 5 V at the initial state of programming and erasing operations. However, the memory window rapidly decreased after 1000 s from 5 to 1.5 V. The ${\Delta}V_T$ of the NFGM containing ZnO was approximately 2 V at the initial state, but the memory window decreased after 1000 s from 2 to 0.4 V. These results mean that metal-oxide nano-particles have feasibility to apply NFGM devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.981-984
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• 2005

This study is to realize its threshold voltage shift after programming operation in charge trap type SONOS memory by simulation. SONOS devices are charge trap type nonvolatile memory devices in which charge storage takes place in traps in the nitride-blocking oxide interface and the nitride layer. For simulation of their threshold voltage as a function of the memory states, traps in the nitride layer have to be defined. However, trap models in the nitride layer are not developed in commercial simulator. So, we propose a new method that can simulate their threshold voltage shift by an amount of charges induced to the electrodes as a function of a programming voltages and times as define two electrodes in the tunnel oxide-nitride interface and the nitride-blocking oxide interface of SONOS structures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• Journal of the Korean institute of surface engineering
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• v.34 no.5
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• pp.494-498
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• 2001

Ferromagnets(FM)-Al-$O_{x}$ -Ferromagnets (FM) tunneling junctions were evaluated by changing the fabricating conditions of an Al-X$/_{x}$ layer. The junction composed of a thicker Al-$O_{x}$ shows the low resistance and the stable MR ratio about 16% in a wide range of oxidation time. For the junctions with the thinner Al-$O_{x}$ , they showed a fast increase of the barrier width as an increase of an oxidation time and exhibited a strong bias dependence. As oxidation time increased, the coercivity ($H_{c}$ ) of bottom Co layer increased gradually due to the local oxidation of Co bottom layer at a interface. However, the small formation of Co oxide did not largely influence on the deterioration of MR ratio.

• Tunnel and Underground Space
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• v.6 no.2
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• pp.175-183
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• 1996

Linear cutting tests on granite were conducted to evaluated the cutting performance of abrasive water jet(AWJ) using several types of abrasives. The abrasives used in the tests were grarnet, alumimum oxide, and silicon carbide. And one type of granite which is comercially known as "KeuchangSuk" was used as workpiece throughout the tests. The results from the tests were described in terms of cutting depth and abrasive productivity. Authors tried to confirm the effects of the operational parameters of abrasive mass flow rate, water pressure, and traverse speed of nozzle on cutting depth and presented almost all the data obtained in the tests. Abrasive productivity can be defined as the area of kerf wall cut by unit weight of abrasive and is an important factor to evaluated the cutting ability of abrasive and assess the cost effectiveness of an AWJ system. In the tests the maximum abrasive productivities of garnet, alumina, and silicon carbide were about 0.21, 0.24, and 0.20 $\textrm{cm}^2$ respectively under similar operational conditions.onditions.