• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1337-1339
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• 1998

The trench termination scheme is introduced for high voltage devices. The curvature of the depletion region at field limiting ring is critical factor to determine the breakdown voltage. The smooth curvature of the depletion junction alleviate the electric field crowding effect around this region. In the trench field limiting ring, the radius of the depletion region is smaller than conventional field limiting ring, but the distance between every trench is spaced small enough to punchthrough before initiation of local breakdown. The trench field limiting ring on silicon can ne formed by RIE followed by oxidation on side wall surface of the trench, and polysilicon filling. The combined termination of this trench floating field ring and field plate have been designed and analyzed. The breakdown simulation by 2-dimensional TCAD shows that the cylindrical junction breakdown voltage for substrate doping might be 99 percent of the ideal breakdwon voltage for substrate doping concentration of $3\times10^{14}cm^{-3}$ with about $100{\mu}m$ of lateral termination width.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.638-643
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• 2003

Channel width dependence of hot-carrier effect in nMOSFET with shallow trench isolation is analyzed. $I_{sub}$- $V_{G}$ and $\Delta$ $I_{ㅇ}$ measurement data show that MOSFETs with narrow channel-width are more susceptible to the hot-carrier degradation than MOSFETs with wide channel-width. By analysing $I_{sub}$/ $I_{D}$, linear $I_{D}$- $V_{G}$ characteristics, thicker oxide-thickness at the STI edge is identified as the reason for the channel-width dependent hot-carrier degradation. Using the charge-pumping method, $N_{it}$ generation due to the drain avalanche hot-carrier (DAHC) and channel hot-electron (CHE) stress are compared. are compared.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.843-847
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• 2014

In Super Junction (SJ) MOSFETs, charge balance is the most important issue of the SJ fabrication process. In order to achieve the best electrical characteristics, such as breakdown voltage and on-resistance, the N-type and P-type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, which is known as the charge balance condition. In conventional charge balance analysis, based on multi-epi process SJ MOSFETs, analytical model has only N, P pillar width and doping concentration parameter. But applying a conventional charge balance principle to trench filling process, easier than Multi-epi process, is impossible due to the missing of the trench angle parameter. To achieve much more superior characteristics of on-resistance in trench filling SJ MOFET, the appropriate trench angle is necessary. So in this paper, modulated charge balance analysis is proposed, in which a trench angle parameter is added. The proposed method is validated using the TCAD simulation tool.

• Journal of the Korea Safety Management & Science
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• v.11 no.2
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• pp.95-101
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• 2009

The present study is to estimate the effect of wave height affecting at the front face of breakwater systems due to specification of submarine trench such as distance from breakwater to dredged area and width of dredge. The wave diffraction field, which is important hydraulic factor in the ocean, is considered to be two dimensional(2D) plane and the configuration of the submarine dredge on the sea bed designated by single horizontal long-rectangular pit system according to the various specific conditions of dredged locations. The numerical simulation is performed by using Green function based on the boundary integral equation and meshed at moving boundary conditions. The results of present numerical simulations are illustrated by applying the normal incidence. It is shown that the ratios of wave height at the front face of breakwater was varied by dependance of distant from breakwater to dredged area and width of dredge. It means that, when the navigation channel or pit breakwater is dredged on seabed, engineers have to consider the specification of dredge. This study can effectively be utilized for safety assessment to various breakwater systems in the ocean field and provided for safety construction of offshore structure.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.57-63
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• 2006

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of electroplating current density and current mode. At $1.25mA/cm^{2}$ of DC mode, Cu filling ratio higher than 95% was obtained for trench vias of $75{\sim}35{\mu}m$ width. When electroplated at DC $2.5mA/cm^{2}$, Cu filling ratios became inferior to those processed at DC $1.25mA/cm^{2}$. Pulse current mode exhibited Cu filling characteristics superior to DC current mode.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.156-163
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• 2008

We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.65-71
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• 2007

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of the electroplating current density and the speed of a rotating disc electrode (RDE). Cu filling characteristics into trench vias were improved with increasing the RDE speed. There was a Nernst relationship between half width of trench vias of Cu filling ratio higher than 95% and the minimum RDE speed, and the half width of trenches with 95% Cu filling ratio was linearly proportional to the reciprocal of root of the minimum RED speed.

• ETRI Journal
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• v.34 no.1
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• pp.134-137
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• 2012

Power metal-oxide semiconductor field-effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double-diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on-state resistance and breakdown voltage. To overcome the tradeoff relationship, a super-junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on-state resistance of 1.2 $m{\Omega}-cm^2$ at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.

• ETRI Journal
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• v.24 no.5
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• pp.333-340
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• 2002

We propose a new process technique for fabricating very high-density trench MOSFETs using 3 mask layers with oxide spacers and a self-aligned technique. This technique reduces the device size in trench width, source, and p-body region with a resulting increase in cell density and current driving capability as well as cost-effective production capability. We were able to obtain a higher breakdown voltage with uniform oxide grown along the trench surface. The channel density of the trench DMOSFET with a cell pitch of 2.3-2.4 ${\mu}m$ was 100 Mcell/$in^2$ and a specific on-resistance of 0.41 $m{\Omega}{\cdot}cm^2$ was obtained under a blocking voltage of 43 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.350-353
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• 1999

This Paper Presents the optimized design of micro-heaters using 501(Si-on-insulator) substrate and oxide-filled trench structure In order to justify a lumped model approximation and thermal boundary assumptions, two-dimensional FDM(finite difference among which conduction is the dominant heat dissipation path. Compared with no-trenchs on the SOI structure, the micro-heaters with trench structures has properties of low heater loss and good thermal isolation. The simulation results show that the heater loss decreases as the number. width and distance of trenchs increases.