• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.09a
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• pp.59-62
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• 2005

백색 LED 램프를 제조하는 공정에서 램프간의 전기적 개방상태의 절연상태를 유지하기 위해 사파이어 기판 위에 성장된 GaN 계 반도체 에피박막층을 제거하기 위해 유도 결합형 플라즈마 식각 공정을 이용하였다. 4 미크론의 두께를 갖는 GaN 층을 식각하는데 있어 식각 방지 마스킹 물질로 포토레지스트, $SiO_2,\;Si_{3}N_4$ 및 $Al_{2}O_3$를 시험하였다. 동일한 전력 및 가스유량상태에서 $Al_{2}O_3$만 에피층을 보호할 수 있음을 확인하였다.

• Journal of the Korean GEO-environmental Society
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• v.17 no.5
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• pp.27-36
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• 2016

Low Impact Development (LID) techniques are eco-friendly storm water management process for water circulation restoration and non-point pollutant reduction. In this study, four LID techniques (Small constructed wetland, Infiltration trench box, Infiltration trench, Vegetated swale) were selected and installed as a real size at the real site. All facilities were evaluated as monitoring under the real environmental climate situation and an artificial rain with exceeding design rainfall. In various rainfall, runoff reduction efficiency and non-point pollutant removal efficiency are increased to the bigger Surface Area of LID (SA)/Catchment Area (CA) ratio and the bigger Storage Volume of LID (SV)/Catchment Area (CA) ratio. Runoff did not occur at all rainfall event (max. 17.2 mm) in infiltration trench and vegetated swale. But Small constructed wetland was more efficient at less than 10 mm, a efficiency of infiltration trench box was similar at different rainfall. Although different conditions (such as structural material of LID, rainfall flow rate, antecedent dry periods), LID techniques are good effects not only water circulation improvement but also water quality improvement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.149-153
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• 2003

Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.1-8
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• 2003

In this study, the high performance BCD device structure which satisfies the high voltage and fast switching speed characteristics is devised. Through the process and device simulation, optimal process spec. & device spec. are designed. We adapt double buried layer structure, trench isolation process, n-/p-drift region formation and shallow junction technology to optimize an electrical property as mentioned above. This I.C consists of 20V level high voltage bipolar npn/pnp device, 60V level LDMOS device, a few Ampere level VDMOS, 20V level CMOS device and 5V level logic CMOS.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.4
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• pp.210-213
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• 2017

In this paper, we analyzed the structural design and electrical characteristics of a 3.3 kV super junction FS IGBT as a next generation power device. The device parameters were extracted by design and process simulation. To obtain optimal breakdown voltage, we researched the breakdown characteristics. Initially, we confirmed that the breakdown voltage decreased as trench depth increased. We analyzed the breakdown voltage according to p pillar dose. As a result of the experiment, we confirmed that the breakdown voltage increased as p pillar dose increased. To obtain more than 3.3 kV, the p pillar dose was $5{\times}10^{13}cm^{-2}$, and the epi layer resistance was $140{\Omega}$. We extracted design and process parameters considering the on state voltage drop.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.90-93
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STI CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. To resolve these problems, the development of slurry for CMP with high removal rate and high selectivity between each thin films was studied then it can be prevent the reasons of many defects by reasons of many defects by simplification of process that directly apply CMP process to STI structure without the reverse moat pattern process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.3
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• pp.175-184
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• 2001

In this study, the improved throughput and stability in device fabrication could be obtained by applying CMP process to STi structue in 0.18 um semiconductor device. To employ the CMP process in STI structure, the Reverse Moat Process used to be added after STI Fill, as a result, the process became more complex and the defect were seriously increased than they had been,. Removal rate of each thin film in STI CMP was not uniform, so, the device must have been affected. That is, in case of excessive CMP, the damage on the active area was occurred, and in the case of insufficient CMP nitride remaining was happened on that area. Both of them deteriorated device characteristics. As a solution to these problems, the development of slurry having high removal rate and high oxide to nitride selectivity has been studied. The process using this slurry afford low defect levels, improved yield, and a simplified process flow. In this study, we evaluated the 'High Selectivity Slurry' to do a global planarization without reverse moat step, and also we evaluated EPD(Eend Point Detection) system with which 'in-situ end point detection' is possible.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.190-195
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• 1995

The feature scale model for selective chemical vapor deopsition process was proposed and the simulation was performed to study the selectivity and uniformity of deposited thin film using Monte Carlo method and string algorithm. The effect of model parameters such as sticking coefficient, aspect ratio, and surface diffusion coefficient on the deposited thin film pattern was improved for lower sticking coefficient and higher aspect ratio. It was revealed that the selectivity loss ascrives to the surface diffusion. Different values of sticking coefficients on Si and on SiO2 surface greatly influenced the deopsited thin film profile. In addition, as the lateral wall angle decreased, the selectively deposited film had improved uniformity except the vicinity of trench wall. The optimum eondition for the most flat selective film deposition pattern is the case with low sticking coefficient and slightly increased surface diffusion coefficient.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.54-57
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• 2001

We studied the characteristics of polishing pad, which can apply STI-CMP process for global planarization of multilevel interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was defected less than 2 on JRlll pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and devise yield.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1050-1053
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• 2002

This paper presents metal structure that is fabricated using UV-LIGA process with PMER N-CA3000. In order to fabricate metal structure with high aspect ratio, the systematic optimization method was adopted and then the structure of $36{\mu}m$ thick mold with aspect ratio 7:1 (trench) and $32{\mu}m$ thick nickel structure was obtained. This structure is applied to the fabrication of optical switch.