• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.33-36
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP nprocess, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.52-52
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• 2009

To date, chalcogenide alloy such as $Ge_2Sb_2Te_5$(GST) have not only been rigorously studied for use in Phase Change Random Access Memory(PRAM) applications, but also temperature gap to make different states is not enough to apply to device between amorphous and crystalline state. In this study, we have investigated a new system of phase change media based on the In-Sb-Te(IST) ternary alloys for PRAM. IST chalcogenide thin films were prepared in trench structure (aspect ratio 5:1 of length=500nm, width=100nm) using Tri methyl Indium $(In(CH_3)_4$), $Sb(iPr)_3$ $(Sb(C_3H_7)_3)$ and $Te(iPr)_2(Te(C_3H_7)_2)$ precursors. MOCVD process is very powerful system to deposit in ultra integrated device like 100nm scaled trench structure. And IST materials for PRAM can be grown at low deposition temperature below $200^{\circ}C$ in comparison with GST materials. Although Melting temperature of 1ST materials was $\sim 630^{\circ}C$ like GST, Crystalline temperature of them was ~$290^{\circ}C$; one of GST were $130^{\circ}C$. In-Sb-Te materials will be good candidate materials for PRAM applications. And MOCVD system is powerful for applying ultra scale integration cell.

• Transactions on Electrical and Electronic Materials
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• v.5 no.5
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• pp.169-172
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• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• Journal of Powder Materials
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• v.20 no.2
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• pp.120-124
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• 2013

This study is carried out to develop the new process for the fabrication of ultra-fine electrodes on the flexible substrates using superhydrophobic effect. A facile method was developed to form the ultra-fine trenches on the flexible substrates treated by plasma etching and to print the fine metal electrodes using conductive nano-ink. Various plasma etching conditions were investigated for the hydrophobic surface treatment of flexible polyimide (PI) films. The micro-trench on the hydrophobic PI film fabricated under optimized conditions was obtained by mechanical scratching, which gave the hydrophilic property only to the trench area. Finally, the patterning by selective deposition of ink materials was performed using the conductive silver nano-ink. The interface between the conductive nanoparticles and the flexible substrates were characterized by scanning electron microscope. The increase of the sintering temperature and metal concentration of ink caused the reduction of electrical resistance. The sintering temperature lower than $200^{\circ}C$ resulted in good interfacial bonding between Ag electrode and PI film substrate.

• Journal of Korean Society of Water and Wastewater
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• v.24 no.6
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• pp.691-701
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• 2010

As the water-cycle is transformed by increasing of the impermeable area in process of urbanization, decentralized rainwater management facilities(infiltration, harvesting and retention facilities) as source control are considered to be a method of restoring water-cycle of urban and reducing runoff. SWMM model was used to analyse the change of water-cycle structure before and after development in A new town watershed. Modified SWMM code was developed to apply infiltration facilities. The modified SWMM was used to analyse the change of water-cycle before and after infiltration trench setup in AJ subcatchment. Changes of the impervious area by development and consequent increase in runoff were analyzed. These analyses were performed by a day rainfall during ten years from 1998 to 2007. According to the results, surface runoff increased from 51.85% to 65.25 %, and total infiltration volume decreased from 34.15 % to 21.08 % in A newtown watershed. If more than 80 infiltration trenches are constructed in AJ subcatchment, the low flow and the drought flow increases by around 47%, 44%, separately. The results of this study, infiltration trench is interpreted to be an effective infiltration facility to restore water-cycle in new town.

• Journal of IKEEE
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• v.11 no.4
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• pp.235-238
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• 2007

The planar edge termination techniques of field-ring and deep junction field-ring were investigated and optimized using a two-dimensional device simulator TMA MEDICI. By trenching the field ring site which would be implanted, a better blocking capability can be obtained. The results show that the p-n junction with deep junction field-ring can accomplish near 30% increase of breakdown voltage in comparison with the conventional field-rings. The deep junctionfield-rings are easy to design and fabricate and consume same area but they are relatively sensitive to surface charge. Extensive device simulations as well as qualitative analyses confirm these conclusions.

• Multiscale and Multiphysics Mechanics
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• v.1 no.3
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• pp.225-231
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• 2016

The formation of silicon-on-nothing (SON) structure during an annealing process from the silicon substrate including the trench structures has been considered as an effective technique to construct the structure that has an empty space under the closed flat surface. Previous studies have demonstrated the mechanism of the formation of SON structure, which is based on the surface diffusion driven by the minimization of their surface energy. Also, it has been fragmentarily shown that the morphology of SON structure can be affected by the initial design of trench (e.g., size, number) and the annealing conditions (e.g., temperature, pressure). Based on the previous studies, here, we report a comprehensive study for the design of the cavity-embedded structure (i.e., SON structure). To do this, a dynamic model has been developed with the phase field approach. The simulation results represent that the morphology of SON structures could be detailedly designed, for example the position and thickness of cavity, the thickness of top and bottom layer, according to the design parameters. This study will give us an advantage in the effective design of SON structures.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.65-65
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• 2003

Chemical mechanical polishing (CMP) is one of the most important processes in recent ULSI (Ultra Large Scale Integrated Circuit) manufacturing technology. Recently, ceria slurries with surfactant have recently been used in STI-CMP,[1] became they have high oxide-to-nitride removal selectivity and widen the processing margin The role of the abrasives, however, on the effect of planarization on STI-CMP is not yet clear. In this study, we investigated how the crystal characteristic affects the planarization efficiency of wafer surface with controlling crystallite size and poly crystalline abrasive size independently.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.