• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.20-25
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• 2005

A high performance Viterbi decoder is designed using modified register exchange scheme and block decoding method. The elimination of the trace-back operation reduces the operation cycles to determine the merging state and the amount of memory. The Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoding methods in block decoding architectures. The elimination of trace-back also reduces the power consumption for finding the merging state and the access to the memory. The proposed decoder can be designed with emphasis on either efficient memory or low latency. Also, it has a scalable structure so that the complexity of the hardware and the throughput are adjusted by changing a few design parameters before synthesis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1803-1811
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• 2001

In this paper, Forward Error Correction(FEC) that is satisfied with ITU-T Recommendation J.83, Annex B(North American Data Over Cable Service Interface Specifications(DOCSIS) for Multimedia Cable Network System(MCNS)) is analyzed. The FEC consist of Reed-Solomon(RS) layer, interleaving layer, randomization layer, and trellis coded modulation(TCM) layer. The effects of quantization of input symbol and of trace-back depth in the Viterbi decoder are simulated over AWGN channels.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1627-1630
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• 2002

본 논문은 역추적 예견 알고리즘을 사용한 비터비 복호기에서의 TB단의 Polling 구조의 단순화 방법을 제시한다. 비터비 복호기의 3대 Unit중 하나인 Trace Back에서 역추적 예견 알고리즘을 사용할 경우 복호화 시점에서의 최소 State Metric 값을 찾아야 하는 번거로움을 줄일 수 있다. 하지만 복호 신호의 신뢰도 분산에 따라 Polling Unit 이 추가되어야 함에 따라 실제 하드웨어 복잡도에서의 이득은 미미한 것으로 알려져 있다. 제시된 구조에서는 Polling Unit을 단순화 할 수 있는 방법을 적용하였다. 기존 하드웨어와의 비교 평가를 위하여 IEEE802.11a의 표준에 따른 부호화율 1/2, 구속장 7을 갖는 비터비 디코더에 대하여 역추적 예견 알고리즘과 파이프라인 구조만을 갖는 경우와 제안된 단순화한 Polling Unit을 적용한 구조와의 비교에서 Trace Back Unit에서 약 45%의 감소 효과를 보였다.

• Korean Journal of Optics and Photonics
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• v.1 no.2
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• pp.217-222
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• 1990

A general ray tracing scheme has been developed for using a personal computer which trace finite rays through any non-rotationally symmetric system. This scheme may be used for the surface type such as conic section with or without aspherics, toric surfaces, sagittal and tangential cylindrical sections and axicons. Specially, any combinational of decentered, tilted and rotated surfaces has been considered. Before transfering to the next surfaces, the local coordinates are refered back to an initial reference coordinate system. We can get a mathmtical model of a non-rotationally symmetrical finite ray trace running on an inexpensive personal computer.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.397-409
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• 2003

This paper describes an implementation of radix-4 trellis parallel architecture and backward state transition control trace back Viterbi decoder, and presents the application results to high speed wireless LAN. The radix-4 parallelized architecture Vietrbi decoder can not only improve the throughput with simple structure, but also have small processing delay time and overhead circuit compared to M-step trellis architecture one. Based on these features, this paper addresses a novel Viterbi decoder which is composed of branch metric computation, architecture of ACS and trace back decoding by sequential control of backward state transition for the implementation of radix-4 trellis parallelized structure. With the proposed architecture, the decoding of variable code rate due to puncturing the base code can easily be implemented by the unified Viterbi decoder. Moreover, any additional circuit and/or peripheral control logic are not required in the proposed decoder architecture. The trace back decoding scheme with backward state transition control can carry out the sequential decoding according to ACS cycle clock without additional circuit for survivor memory control. In order to evaluate the usefulness, the proposed method is applied to channel CODEC of the IEEE 802.11a high speed wireless LAN, and HDL coding simulation results are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.14-23
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• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2001.12a
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• pp.267-270
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• 2001

In this paper, we propose the self-autonomous algorithm for mobile robot system. The proposed mobile robot system which is teamed by learning with the neural networks can trace the target at the same distances. The mobile robot can evaluate the distance between robot and target with ultrasonic sensors. By teaming the setup distance, current distance and command velocity, the robot can do intelligent self-autonomous drive. We use the neural network and back-propagation algorithm as a tool of learning. As a result, we confirm the ability of tracing the target with proposed mobile robot.

• Journal of the Korean Society of Propulsion Engineers
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• v.25 no.2
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• pp.55-65
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• 2021

In this study, the design criteria is presented for Finocyl grain, which is easy to generate neutral thrust when designing solid rocket motors. For this purpose, an automated program using drafting method was developed for burn-back analysis and its accuracy was validated. Using this developed program, burn-back analysis was performed with various configuration parameters of Finocyl grain, and the tendency and sensitivity analysis on burning characteristics were performed. Based on this analysis, the design criteria were presented to generate the neutral burning surface area trace for a Finocyl grain.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.46 no.5
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• pp.638-648
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• 2013

To understand the geochemical characteristics of intertidal sediment in a semi-enclosed bay, we measured various geochemical parameters, including grain size, ignition loss (IL), chemical oxygen demand (COD), acid volatile sulfide (AVS), and trace metals (Al, Fe, Cu, Pb, Zn, Cd, Hg, and As), in intertidal sediment from three bays (Deukryang Bay, Yeoja Bay, and Gamak Bay) in the southern region of Jeollanam Province. The intertidal sediment in Deukryang Bay consisted of various sedimentary types, such as sand, gravelly muddy sand, mud, and silt, whereas the intertidal sediments in Yeoja and Gamak Bays were composed mainly of mud. The concentrations of IL, COD, AVS and trace metals in the intertidal sediments of the three study regions were relatively high near areas affected by input of stream waters and/or shellfish farming waste. The concentrations of organic matter and trace metals in Gamak Bay were much higher than those in Deukryang and Yeoja Bays, which appears to be due to the influence of anthropogenic pollutants, originating from the city and the industrial complex near Gamak Bay. The evaluation results of organic matter and metal pollution using the sediment quality guidelines showed that the intertidal sediments in the three study regions were not polluted in terms of organic matter and trace metals. In future, sustainable management for sources of organic matter and trace metal is necessary to conserve a healthy benthic ecosystem in intertidal sediments.