• 제어로봇시스템학회논문지
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• 제17권11호
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• pp.1125-1131
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• 2011

This paper presents a control theoretic approach to realizing fault tolerance in asynchronous sequential circuits. The considered asynchronous circuit is assumed to work in space environment and is subject to faults caused by total ionizing dose (TID) effects. In our setting, TID effects cause permanent changes in state transition characteristics of the asynchronous circuit. Under a certain condition of reachability redundancy, it is possible to design a corrective controller so that the closed-loop system can maintain the normal behavior despite occurrences of TID faults. As a case study, the proposed control scheme is applied to an asynchronous arbiter implemented in FPGA.

• 전기전자학회논문지
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• 제27권3호
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• pp.303-307
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• 2023

본 논문은 Buried Channel Array Transistor(BCAT) 소자의 Oxide 내부에 Total Ionizing Dose(TID) effects으로 인한 Electron-Hole Pair의 생성이 유도되어, Oxide 계면의 Hole Trap Charge의 증가에 따른 누설전류의 증가와 문턱 전압의 변화를 기존에 제안한 Partial Isolation Buried Channel Array Transistor(Pi-BCAT)구조와 비교 시뮬레이션 하여, Pi-BCAT 소자의 증가한 Oxide 면적과 상관없이 변화한 누설전류와 문턱 전압에서의 특성이 비대칭 도핑 BCAT 구조보다 우수함을 보여 준다.

• 한국우주과학회:학술대회논문집(한국우주과학회보)
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• 한국우주과학회 2005년도 한국우주과학회보 제14권1호
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• pp.143-147
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• 2005

우주시스템 연구실에서 개발 중인 HAUSAT-2의 우주방사능 환경은 포획된 양자와 전자, 태양양성자이다. 본 논문에서는 우주방사능 환경에 대해 임무기간동안의 총 피폭량을 계산하였고, 총 피폭량에 대해 HAUSAT-2에서 사용하는 부품들의 부품의 우주방사능 허용레벨 분류과정을 통해 사용가능성을 검증하였다. 또한 단일사건 발생확률을 계산하여 단일사건 발생에 대비하는 시스템을 설계에 반영하였다.

• Journal of Semiconductor Engineering
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• 제1권3호
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• pp.81-87
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• 2020

An instrumentation amplifier (IA) and an analog-to-digital converter (ADC) are essential circuit blocks for accurate and robust sensor readout systems. This paper introduces recent advances in radiation-hardening by design (RHBD) techniques applied for the sensor readout integrated circuits (IC), e.g., the three-op-amp IA and the successive-approximation register (SAR) ADC, operating against total ionizing dose (TID) and singe event effect (SEE) in harsh radiation environments. The radiation-hardened IA utilized TID monitoring and adaptive reference control to compensate for transistor parameter variations due to radiation effects. The radiation-hardened SAR ADC adopts delay-based double-feedback flip-flops to prevent soft errors which flips the data bits. Radiation-hardened IA and ADC were verified through compact model simulation, and fabricated CMOS chips were measured in radiation facilities to confirm their radiation tolerance.

• 한국시뮬레이션학회논문지
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• 제19권4호
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• pp.123-128
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• 2010

본 논문에서는 우주방사능 환경에서 우주방사능/총 누적 방사선량(TID) 및 이에 대한 시스템 영향과 정지궤도 위성 시스템 설계를 Spenvis 를 사용하여 분석하였다. 우주환경에서 정지궤도 위성 시스템이 겪게 될 우주방사선 환경을 포획된 입자, 태양 양성자 그리고 우주선으로 구분하여 각각 NASA AP8, JPL91 그리고 NRL CREME 모델을 사용하여 전산모사하였다. 임무수명기간 동안 전자부품에 계속적으로 피폭되는 전체 방사량을 알루미늄 차단두께의 함수로 나타내었으며, 이 값들은 디지털채널 처리부의 전자부품의 선택기준 및 위성체 또는 구성품의 구조물 두께를 설정할 수 있는 기준으로 제시한다.

• 전기학회논문지
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• 제66권3호
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• pp.540-544
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• 2017

In this study, we analyzed the effects of TID(Total Ionizing Dese) and TREE(Transient Radiation Effects on Electronics) on nMOSFET and pMOSFET fabricated by 0.18um CMOS process. The size of nMOSFET and pMOSFET is 100um/1um(W/L). The TID test was conducted up to 1 Mrad(Si) with a gamma-ray(Co-60). During the TID test, the nMOSFET generated leakage current proportional to the applied dose, but that of the pMOSFET was remained in a steady state. The TREE test was conducted at TEST LINAC in Pohang Accelerator Laboratory with a maximum dose-rate of $3.16{\times}10^8rad(si)/s$. In that test nMOESFET generated a large amount of photocurrent at a maximum of $3.16{\times}10^8rad(si)/s$. Whereas, pMOSFETs showed high TREE immunity with a little amount of photocurrent at the same dose rate. Based on the results of this experiment, we will progress the research of the radiation hardening for CMOS unit devices.

• Journal of Astronomy and Space Sciences
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• 제33권3호
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• pp.229-236
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• 2016

We present proton-induced single event effects (SEEs) and γ-ray-induced total ionizing dose (TID) data for 1 Gbit lowpower double data rate synchronous dynamic random access memory (LPDDR SDRAM) fabricated on a 5 μm epitaxial layer (54 nm complementary metal-oxide-semiconductor (CMOS) technology). We compare our radiation tolerance data for LPDDR SDRAM with those of general DDR SDRAM. The data confirms that our devices under test (DUTs) are potential candidates for space flight applications.

• 전기학회논문지
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• 제67권6호
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• pp.745-752
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• 2018

ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.

• Nuclear Engineering and Technology
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• 제54권11호
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• pp.3985-3995
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• 2022

The emergence of new nanoscale technologies has imposed significant challenges to designing reliable electronic systems in radiation environments. A few types of radiation like Total Ionizing Dose (TID) can cause permanent damages on such nanoscale electronic devices, and current state-of-the-art technologies to tackle TID make use of expensive radiation-hardened devices. This paper focuses on a novel and different approach: using machine learning algorithms on consumer electronic level Field Programmable Gate Arrays (FPGAs) to tackle TID effects and monitor them to replace before they stop working. This condition has a research challenge to anticipate when the board results in a total failure due to TID effects. We observed internal measurements of FPGA boards under gamma radiation and used three different anomaly detection machine learning (ML) algorithms to detect anomalies in the sensor measurements in a gamma-radiated environment. The statistical results show a highly significant relationship between the gamma radiation exposure levels and the board measurements. Moreover, our anomaly detection results have shown that a One-Class SVM with Radial Basis Function Kernel has an average recall score of 0.95. Also, all anomalies can be detected before the boards are entirely inoperative, i.e. voltages drop to zero and confirmed with a sanity check.

• 한국전기전자재료학회논문지
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• 제37권5호
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• pp.507-511
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• 2024

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.