• 제목/요약/키워드: Timing phase

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Frame synchronization Confirmation Technique Using Pilot Pattern

  • Song, Young-Joon
    • Journal of Communications and Networks
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    • v.2 no.1
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    • pp.69-75
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    • 2000
  • A new frame synchronization confirmation technique using a pilot pattern of both uplink and downlink channels is proposed for W-CDMA (Wideband Code Division Multiple Access) system. It is shown that by using this technique, we can cancel the side lobe for autocorrelation functions of the frame synchronization words of pilot pattern have the maximum to-of-phase autocorrelation value "4" with two peak values equal in magnitude and opposite in polarity at zero and middle shifts. Due to this side lobe cancellation effect, therefore, the autocorrelation function of the frame synchronization words becomes ideal for the frame synchronization confirmation since double maximum correlation values equal in magnitude and opposite polarity at zero ad middle shifts can be achieved. This property can be used to double check frame synchronization timing and thus. improve the frame synchronization confirmation performance.

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Heuristics for Synchronization of Production and Transportation Planning in the Supply Chain (공급사슬에서 생산 및 물류의 동기화를 위한 발견적 기법)

  • Jeong Jeong-U;Lee Yeong-Hae
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 2006.05a
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    • pp.159-166
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    • 2006
  • The aim of synchronization of production and transportation planning in the supply chain is to increase the flexibility and to decrease various costs. The suggested model in this study synchronizes the timing to supply to a downstream manufacturer directly after production and to be consumed in a downstream manufacturer right after receipt. This model deals with the frequent delivery in small amount which is a new trend of the transportation not governed the economy of scale principle. Moreover, various types of transportation governed by the economy of scale principle or not are considered. Then, the two-phase mathematical model is suggested to obtain optimal job sequence and production quantity for each tasks. But, it is difficult to gain optimal solutions if there is a transportation governed by the economy of scale principle in the supply chain, or the size of the problem is increased. Thus, heuristic algorithms based on simulated annealing and genetic algorithm are suggested to find good solutions in the reasonable time.

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An Efficient Simulation Technique to Verify Real-time Performance of Vehicle Control Systems (자동차 제어 시스템의 실시간 성능 검증을 위한 효율적인 실시간 시뮬레이션 기법)

  • Kim, Seunggon;We, Kyoung-Soo;Lee, Chang-Gun;Yi, Kyongsu
    • Journal of Institute of Control, Robotics and Systems
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    • v.21 no.3
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    • pp.187-193
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    • 2015
  • When developing a vehicle control system, simulation methods are widely used to validate the whole system in the early development phase. With this regard, the simulator should correctly behave just like the real parts that are not yet implemented while interacting with already implemented parts in real-time. However, most simulators cannot provide functionally and temporally accurate behaviors of the target system. In order to overcome this limitation, this paper proposes a novel real-time simulation technique that can efficiently simulate the temporal behavior as well as the functional behavior of the simulation target system.

VLSIs for the MAC TV System - Part III. A Data and Clock Recovery Circuit (MAC 방식 TV 시스템용 IC의 설계 - III. 신호 및 클럭 복원기)

  • Moon, Yong;Jeong, Deog-Kyoon
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.12
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    • pp.1644-1651
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    • 1995
  • A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

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High-Robust Relaxation Oscillator with Frequency Synthesis Feature for FM-UWB Transmitters

  • Zhou, Bo;Wang, Jingchao
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.2
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    • pp.202-207
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    • 2015
  • A CMOS relaxation oscillator, with high robustness over process, voltage and temperature (PVT) variations, is designed in $0.18{\mu}m$ CMOS. The proposed oscillator, consisting of full-differential charge-discharge timing circuit and switched-capacitor based voltage-to-current conversion, could be expanded to a simple open-loop frequency synthesizer (FS) with output frequency digitally tuned. Experimental results show that the proposed oscillator conducts subcarrier generation for frequency-modulated ultra-wideband (FM-UWB) transmitters with triangular amplitude distortion less than 1%, and achieves frequency deviation less than 8% under PVT and phase noise of -112 dBc/Hz at 1 MHz offset frequency. Under oscillation frequency of 10.5 MHz, the presented design has the relative FS error less than 2% for subcarrier generation and the power dissipation of 0.6 mW from a 1.8 V supply.

LPM Control by $\mu$-Step drive method ($\mu$-Step 구동방식에 의한 LPM의 제어)

  • Baek, S.H.;Youn, S.Y.;Kim, Y.;Im, T.B.;Kim, C.J.
    • Proceedings of the KIEE Conference
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    • 1995.11a
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    • pp.287-289
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    • 1995
  • In this paper, We applied the $\mu$-stepping method on the Phase Excitation Sequence of Hybrid type LPM. Linear Pulse Motor can opeate in an open loop control as an effective positioning actuator. PWM driver was used for low power loss and automatically adjusted voltage at rate current. Finally we find that through the position-velocity for timing Triangular and Trapezoidal Profile are very affected by velocity and acceleration parameter.

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Symbol timing synchronization for OFDM by using QPSK modulation (QPSK변조를 이용한 OFDM 시스템의 심볼 타이밍 동기)

  • Kang, Eun-Su;Lim, Chae-Hyun;Han, Dong-Seog
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2006.11a
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    • pp.171-174
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    • 2006
  • OFDM(orthogonal frequency division modulation)은 주파수 선택적인 페이딩 환경에서 높은 전송율과 빠른 속도를 가지는 효율적인 전송 기법이다. 그러나 OFDM 심볼이 시작되는 지점을 정확히 찾지 못하면 시간 영역에서 위상회전으로 인해 수신 데이터의 BER(bit error rate)이 높아질 수 있다. QPSK(quadrature phase shift king)변조를 이용한 OFDM 시스템에선 정수배의 샘플 옵셋만 아니라 소수배의 샘플 옵셋까지 보상하여 동기를 획득해야 한다. QPSK 심볼 복조 시 소수배의 샘플 옵셋이 잔존할 경우 시스템의 수신 성능은 떨어지기 때문이다. 본 논문에서는 QPSK변조를 이용한 OFDM 시스템에서 소수배의 샘플 옵셋이 존재할 경우 동기를 획득하는 방법에 대해 제안한다. 본 논문에서 제안된 심볼 타이밍 동기 방법은 수신된 트레이닝 심볼의 상관관계를 이용하여 0.5 샘플 이전과 이후의 충격응답을 각각 구하여 이들을 차를 이용하여 동기를 획득한다. 제안한 심볼 타이밍 동기 기법의 성능은 멀티패스의 모델화 채널을 적용한 모의실험을 통하여 검증하였다.

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Oral signs of acute leukemia for early detection

  • Lim, Hyun-Chang;Kim, Chang-Sung
    • Journal of Periodontal and Implant Science
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    • v.44 no.6
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    • pp.293-299
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    • 2014
  • Purpose: Systemic disease can manifest oral signs at an early phase, which may be crucial for the diagnosis and timing of treatment. This report describes two patients who presented with gingival enlargement as an early sign of acute leukemia. Methods: Two patients presented with oral symptoms including severe gingival enlargement. The progress of their symptoms was associated with underlying systemic disease. Results: The patients were transferred to the Department of Hematology and diagnosed with acute myelomonocytic leukemia. They received appropriate treatment and survived. Conclusions: Gingival enlargement can be caused by underlying systemic diseases. Accurate diagnosis and timely referral are important for preventing a fatal situation. It must be emphasized that some oral signs and symptoms may be closely correlated with systemic diseases.

Performance Analysis of Hybrid Interference Cancellation Scheme with Timing or Phase Errors over Rayleigh Fading Channel (레일레이 감쇄 채널에서 타이밍 또는 위상 오류를 갖는 혼합 간섭 제거 기법의 성능 분석)

  • 전성진;박상규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.12A
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    • pp.1787-1795
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    • 2000
  • 이 논문에서는 레일레이 감쇄 채널에서 타이밍 또는 위상 오류를 갖는 혼합 간섭 제거 기법을 이용한 DS/CDMA 시스템의 평균 비트 오류 확률을 분석한다. 유도한 결과를 타이밍 또는 위상 오류를 갖는 일반 상관 수신기의 평균 비트 오류 확률과 비교 분석한다. 평균 비트 오류 확률은 정규 근사법을 이용하여 유도하며, 칩 시간에 대한 타이밍 오류의 비, 위상 오류의 정도, Eb/No에 따라 혼합 간섭 제거 기법을 이용한 수신기의 성능을 분석한다. 혼합 간섭 제거 기법을 이용한 수신기의 평균 비트 오류 확률은 타이밍 또는 위상 오류에 의해 증가하나 타이밍 또는 위상 오류가 작은 경우 오류가 없는 일반 상관 수신기에 비해 성능이 크게 개선된다.

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A study on the synchronization parameter to design ADSL chip in DMT systems (DMT시스템에서 ADSL 칩 설계를 위한 동기화 파라미터에 관한 연구)

  • Cho, Byung-Lok;Park, Sol;Kim, Young-Min
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.3 no.3
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    • pp.687-694
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    • 1999
  • In this paper, to draw out the parameter of synchronization for ADSL(Asymmetric Digital Subscriber Line) chip design, we analyze the performance of STR(Symbol Timing Recovery) and frame synchronization with computer simulation. We analyze and design PLL(Phase Lock Loop) loop for ADSL. As a result, we obtained the optimum parameter of STR to design ADSL chip. Also, when performed frame synchronization with several algorithm, we analyzed the performance of FER(Frame Error Rate) and the effect of frame offset with computer simulation.

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