• Archives of design research
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• v.19 no.5 s.67
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• pp.335-350
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• 2006

Due to the development in industrial technology, changes in consumer behavior and aggravating competition within the industry, it is growing only harder every day to build up a strong brand power. Besides, a brand is supposed to age as time goes by, following a brand life cycle, as it is not a solid, immutable asset but something of a living creature. Therefore, self-renovation and revitalization efforts are needed, in order to incessantly confirm the self existence through the relationship with the consumer. In sum, revitalization operation is needed to renew a brand that has grown trite in the passage of time or due to the change in market condition, so as to bring it back anew to the consumers. This study did not stop at measuring the effect of a design renewal as a short-term assignment, but focused on the long-term brand management following the brand life cycle and aimed to define the effective timing and method of revitalization by comprehending the analysis results of consumer consciousness by analyzing the successful cases of brand revitalization and selecting the research analysis targets. As a result, this study proved that a properly-timed brand revitalization efforts in order to cope in advance with predictable changes in environment, can significantly prevent any drop of brand equity from occurring and then extend the brand life cycle. Also, this study could find that a brand revitalization is not a mere concept of a strategy for a short-term sales increase, but should be a long-term strategy to manage a brand, which must be practiced continuously in the time when the brand life cycle curve starts to fall. This research could also confirm that a superficial design renewal, which changes only the packaging of a brand, peformed in short-term haste, is not of help at all.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1380-1386
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• 2009

In this paper, we propose a CQS(Calendar Queue Scheduler) architecture which was designed for processing multimedia and timing traffic in home network. With various characteristics of the increased traffic flowed in home such as VoIP, VOD, IPTV, and Best-efforts traffic, the needs of managing QoS(Quality of Service) are being discussed. Making a group regarding application or service is effective to guarantee successful QoS under the restricted circumstances. The proposed design is aimed for home gateway corresponding to the end points of receiver on end-to-end QoS and eligible for supporting multimedia traffic within restricted network sources and optimizing queue sizes. Then, we simulated the area for each module and each memory. The area for each module is referenced by NAND($2{\times}1$) Gate(11.09) when synthesizing with Magnachip 0.18 CMOS libraries through the Synopsys Design Compiler. We verified the portion of memory is 85.38% of the entire CQS. And each memory size is extracted through CACTI 5.3(a unit in mm2). According to the increase of the memory’sentry, the increment of memory area gradually increases, and defining the day size for 1 year definitely affects the total CQS area. In this paper, we discussed design methodology and operation for each module when designing CQS by hardware.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.5
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• pp.47-53
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• 2020

The purpose of this study was to increase product reliability by improving the durability of the breech block for a 30mm Automatic Gun. The breech block is a key component of a gun that functions as chambering, closing, and extracting. The breech block requires high reliability, which needs to be improved because cracks of a breech block can occur early in operation. Cause analysis confirmed that the crack is caused by repeated impacts. Therefore, the following improvement measures were studied, and the effects were demonstrated using a firing test. The energy of impact absorption was increased by changing the material, and the stress concentration was mitigated by increasing the value of R. In addition, the fatigue life was increased by adding Shot-peening, deleting chromium plating, and changing the forging method. The firing test did not show firing trouble for up to 5,000 rounds. The start timing of the crack was delayed, and the depth was small. Therefore, the improved product was more durable than the existing product. This study can be used as a useful reference when assessing the improvement of the durability of similar products, life study, and criteria for crack acceptance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.3 no.3
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• pp.19-26
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• 1983

Through traffic utilization of left turn lane constitutes an unique traffic operation at an intersection. Consequently, due to the provision as of current practice, conventional methods which estimate traffic volume and intersection capacity by lane would not be valid for design of signal timings. Through traffic utilization factor of left turn lane is affected by left turn volume and signal timings. The primary purpose of this study is to compare the results from leading left turn green phasing scheme with those from previously studied lagging left turn green phasing scheme in terms of utilization factor and intersection capacity by various left turn volume and signal timings, and thereby optimum signal timing to maximize the capacity at given left turn volume. Leading left turn green phasing increases capacity by 10~15 % as compared with that for current lagging left turn green phasing scheme. The range of optimum cycle length for left turn volume about 150 vph is 180~200 second. This cycle length range and left turn interval are longer than those for the lagging left turn green phasing scheme.

• KEPCO Journal on Electric Power and Energy
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• v.2 no.4
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• pp.577-582
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• 2016

This Study focused on the development of SMPS (Switching Mode Power Supply) to supply the constant votage and current nevertheless LED fluorescent Light generated the electric noise (with Harmonics) and Inrush current at instant time of turn-on and off. Recently, according to the Green policy in government, the LED fluorescent Lighter showed the rapidly increasing tend as indoor and outdoor Lighter. But, because of costs, LED fluorescent Light not considered and neglected the following items; power factor, efficiency, Harmonics and Inrush current. So, we are developed the SMPS about 3 key issues as follows: 1st, power factor and efficiency is 85%. 2nd, the switching noisy by harmonic is minimized. 3rd, the Inrush current at turn on and off time is reduced the minimum 0.3 A after $100{\mu}sec$ on turnon time. The proposed SMPS adjusted by LNK 409 driver (included the high frequency modulation function). Although, the developed SMPS maintained the about 85% of power factor and efficiency. but, the SMPS must be generated low heat by the variation of minute load current at switching timing. To improve the above weak point, the developed SMPS have the feedback monitoring circuit between input side and output side to maintain the power factor and efficiency. Also, we are studied the time-constant of control circuit to output the constant voltage and current nevertheless the load disturbance of LED lighting. The LED fluorescent Light of 46W is checked the above items.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.12 no.2
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• pp.63-75
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• 2013

Roundabouts have been operated in Europe, America and Australia since the 1970s, and many relevant researches continually was carried out. Though many studies regarding roundabout have been recently conducted in korea, most of them have focused on its operational safety and efficiency. Moreover, roundabout design guideline did not define a clear criteria related to pedestrian in roundabout, but seldom investigate the influences of pedestrian on crosswalk. In this study, we seek ways to operate the pedestrian crosswalk signal on roundabout maximizing their operational effects in exceptional case such as rush hour or intersection near the special facilities. We proved that roundabout signal operation is effective under certain circumstances in according to the number of pedestrian, and suggested the optimal signal timing plan for signalized roundabouts. For pursuing the above, we conducted the simulation test using the VISSIM model. The results show that the operational effectiveness of signalized roundabout was evaluated to be better than non-signalized roundabout in specific pedestrian volume condition. In addition, those results are confirmed using simulation analysis conducted on the real roundabout.

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.4
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• pp.72-81
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• 2006

In this paper, we first define a total of 64 instructions that are considered to be essential and frequently used, construct a datapath diagram, determine the control sequence using a finite state machine, and implement an 8-bit microcontroller using FPGA in VHDL. In the past, only functional simulation results of a rudimentary microcontroller were reported, the microcontroller lacked interrupt handling capability, or it was not implemented in hardware. We have designed a self-contained 8-bit microcontroller such that it can perform data transfer, addition, and logical operations, as well as stack and external interrupt operations. Following timing simulation of the designed microcontroller, we implemented it in an FPGA and verified its operation successfully. The design and implementation has been done under the Altera MAX+PLUS II integrated development environment using the EP1K50TC144-3 chip. The maximum operating frequency, the total number of logic elements used, and the logic utilization were found to be 9.39 MHz, 2813, and 97%, respectively. The result can be used as a microcontroller IP, and as needs arise, the VHDL code can be modified accordingly.