• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.1
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• pp.47-55
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• 1994

This paper investigates the performance analysis of the packet DS/SS receiver with a PJED(phase-jump error detector) using the block signal processing(BSP) methods. The conventional packet DS/SS block receiver has a high probability of mistaking the phase-jump detection, which causes the frequency estimation error. The conventional receiver uses a Matched-Pulse Timing Extractor which has a complicated structure. The proposed packet DS/SS block receiver with the PJED which uses libearity of the phase has little probability of mistaking the phase-jump detection. The proposed Matched Pulse Timing Extractor gas the more simple structure but obtains the same performance on the exact matched-pluse timing as the conventional one does. The simulation results show that the proposed receiver gives about 2dB improvement in the BER compared with the conventional receiver.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.355-361
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• 2007

In this paper, the hop-timing estimator, which NED and ELF are adopted to, has been proposed. The estimation performance of the proposed scheme and the conventional scheme is compared through computer simulations. The simulation results show that the new system has less hop-timing error than the conventional system in partial band noise jamming channel. The lover Eb/Nj and ratio of jamming bandwidth(rho) we, the bigger performance enhancement of the proposed system is.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.12-21
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• 2004

Error control is one of major concerns in many electronic systems. Experience shows that most malfunctions during system operation are caused by transient faults, which often mean abnormal signal delays that may result in violations of circuit element timing constraints. This paper presents a novel CMOS-based concurrent timing error detector that makes a flip-flop to sense and then signal whether its data has been potentially corrupted or not by a setup or hold timing violation. Designed circuit performs a quiescent supply current evaluation to determine timing violation from the input changes in relation to a clock edge. If the input is too close to the clock time, the resulting switching transient current in the detection circuit exceeds a reference threshold at the instant of the clock transition and an error is flagged. The circuit is designed with a $0.25{\mu}m$ standard CMOS technology at a 2.5 V supply voltage. The validity and effectiveness are verified through the HSPICE simulation. The simulation results in this paper shows that designed circuit can be used to detect setup and hold time violations effectively in clocked circuit element.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.2 s.344
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• pp.56-65
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• 2006

In this paper, we introduce modified difference type symbol timing detection method of simple structure and show the relations between S/N ratio and timing detection performance which less influenced by multipath channel delay profile and added noise level and it show very exact GI detection performance characteristics. In the computer simulations, 4 symbol time duration of short and long training of IEEE802.11a standard OFDM frame are used for symbol synchronization timing detection. The computer simulation results show the very exact symbol timing detection performance characteristic within 1 sample error of OFDM signal regardless channel delay profile from minimn phase channels of phase rotation ${\pi}/2$ to non-minimum phase channels of phase rotation ${\pi}/2$ of received OFDM signal and added noise level in channel.

• Journal of Biomedical Engineering Research
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• v.36 no.5
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• pp.169-176
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• 2015

Implantable closed-loop epilepsy controllers require ideally both accurate epileptic seizure detection and low power consumption. On-chip oscillators can be used in implantable devices because they consume less power than other oscillators such as crystal oscillators. In this study, we investigated the tolerable error range of a lower power on-chip oscillator without losing the accuracy of seizure detection. We used 24 ictal and 14 interictal intracranial electroencephalographic segments recorded from epilepsy surgery patients. The performance variations with respect to oscillator frequency errors were estimated in terms of specificity, modified sensitivity, and detection timing difference of seizure onset using Generic Osorio Frei Algorithm. The frequency errors of on-chip oscillators were set at ${\pm}10%$ as the worst case. Our results showed that an oscillator error of ${\pm}10%$ affected both specificity and modified sensitivity by less than 3%. In addition, seizure onsets were detected with errors earlier or later than without errors and the average detection timing difference varied within less than 0.5 s range. The results suggest that on-chip oscillators could be useful for low-power implantable devices without error compensation circuitry requiring significant additional power. These findings could help the design of closed-loop systems with a seizure detector and automated stimulators for intractable epilepsy patients.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1436-1444
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• 2000

In this paper, we propose the joint carrier and symbol timing recovery algorithm using repetitive preamble and differential detection for burst modem. The proposed algorithm can estimate the frequency offset and the symbol timing error regardless of the amount of frequency offset, with a high accuracy, even using very short preamble and at low SNR values. The algorithms for continuous phase frequency shift keying (CPFSK) and phase shift keying (PSK) types are developed. Through computer simulations, we compare the proposed algorithm with the existing algorithms on the estimation accuracy in terms of the preamble length, and analyze those bit error rate(BER) performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.24-30
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• 2007

In this paper, an energy detection-based low power, low complexity IR-UWB receiver in multipath impulse radio channel is presented. The proposed receiver has a simple 1-bit sampler for energy detection. Also, multipath signal received from multipath impulse radio channel is amplified and envelope of the signal is detected. Then, energy detection technique using integrator by summing multipath signals in certain period is adopted to minimize the BER loss by simple energy detection. In particular, in acquisition of a sample signal, SNR is additionally improved using a digital sampler. Symbol decision using several sampled signals is performed and thus the process of symbol synchronization is significantly simplified. Also, it is effectively designed to be compatible with influences of multipath and timing error. In addition, the proposed receiver complexity is reduced using pulse decision window. The performance of the proposed receiver is simulated based on IEEE 802.15.4a channel model and the algorithms are implemented on FPGA.

• Journal of Positioning, Navigation, and Timing
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• v.6 no.4
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• pp.149-157
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• 2017

In this study, a system that precisely determines the heave of ship hull was designed using time-differenced GNSS carrier phase measurement, and the performance was examined. First, a technique that calculates precise position relative to the original position based on TDCP measurement for point positioning using only one receiver was implemented. Second, to eliminate the long-cycle drift error occurring due to the measurement error that has not been completely removed by time-differencing, an easily implementable high-pass filter was designed, and the optimum coefficient was determined through an experiment. In a static experiment based on the precise heave measurement system implemented using low-cost commercial GNSS receiver and PC, the heave could be measured with a precision of 2 cm standard deviation. In addition, in a dynamic experiment where it moved up and down with an amplitude of 48 cm and a cycle of 20 seconds, precise heave without drift error could be determined. The system proposed in this study can be easily used for many applications, such as the altitude correction of fish detection radar.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.11
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• pp.1299-1310
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• 1992

Recently, digital realizations of timing recovery circuits for digital data transmission are of growing interest. As a result of digital realization of timing recovery circuits, new digital algorithms for timing error detection are required. In this paper, we present a new digital Angular Form(AF) algorithm which can be directly applied to QPSK modulation technique. AF algorithm is basically developed on the concepts of detected angle form and transition logic table. We evaluated the performance of this algorithm by Monte-Carlo simulation method under Gaussian and Impulsive noise environments. From the performance evaluation result, we show that the performance of AF Algorithm is better than that of Gardner in BER, RMS jitter, S-curve.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1B
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• pp.24-33
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• 2002

The cell search scheme for W-CDMA consists of the following three stages: slot synchronization(1st stage), group identification and frame boundary detection(2nd stage), and long code identification(3rd stage). The performance of the cell search when a mobile station is switched on, which is referred to as initial cell search, is decreased by the initial frequency and timing error. In this paper, we propose the pipeline structured initial cell search scheme using time trackers to compensate for the impact of the initial timing error in the stage 2 and stage 3. The simulation results show that the performance of the proposed scheme is maximal 1.5dB better than that of the conventional one when the initial timing error is near ${\pm}T_c$/2.