• Title/Summary/Keyword: Timing analysis

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A Study on DPA Countermeasures of the block-type ciphers (블록 형태 암호에서의 DPA 방어기술 연구)

  • 이훈재;최희봉;이상곤
    • Journal of Korea Society of Industrial Information Systems
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    • v.7 no.4
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    • pp.1-8
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    • 2002
  • Attacks have been proposed that use side information as timing measurements, power consumption, electromagnetic emissions and faulty hardware. Elimination side-channel information of prevention it from being used to attack a secure system is an active ares of research. In this paper, differential power analysis techniques used to attack DES are compared and analyzed finally, we propose a software prevention idea of DPA attack for DES-like ciphers.

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Reducing Effect of Residual Vibration Through Command Input Shaped Considering Partial Modes (부분 모드만을 고려하여 성형된 입력을 이용한 잔류 진동의 감소 효과)

  • Jung, Kwangsuk
    • Journal of Institute of Convergence Technology
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    • v.1 no.1
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    • pp.18-23
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    • 2011
  • Shaping an input command through considering the resonant modes of multi degrees of freedom system, it is possible to realize the wanted motion, without exciting the uncontrollable modes of the flexible system. But, an increase of modes to be considered brings inevitably about the time delay due to an excessive rising time. On the purpose of reducing the rising time, only the interesting and dominant modes can be considered to determine the timing pulses of input shaper. In this paper, an effect of shaper by the partial modes is analysed for a specific system and the input shapers by the partial modes are analysed for three d.o.f damped system, using Matlab simulation.

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Model-based specification and static timing-analysis of embedded systems (임베디드 시스템에 대한 모델 기반의 명세 기법 및 정적 시간 분석 기술)

  • Park, Hae-Woo;Kim, Jin-Woo;Ha, Soon-Hoi
    • Proceedings of the Korean Information Science Society Conference
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    • 2007.10b
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    • pp.258-263
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    • 2007
  • 임베디드 시스템은 그 복잡도가 나날이 증가하고 있는데, 특히 기능성 외에 주어진 시간 제약 조건을 만족해야 한다는 점에서 개발 및 검증이 어렵다는 특징을 갖고 있다. 특히 검증에 대해서는 많은 경우에 적당한 시나리오들을 잡아 반복적인 시뮬레이션을 하는 방법을 사용하는데, 이 방법은 많은 시간이 걸리며, 적당한 시나리오들을 잡기 어렵다는 문제 또한 가지고 있다. 본 논문에서는 데이터플로우 모델과 유한상태기계 모델을 확장하여 시스템에 자원 사용 정보 및 시간 제약 조건을 명세하고, 이 모델들에 기반한 정적 시간 분석 방법을 제시하고 있다. 본 논문에서 제시한 방법을 통해 검증 시 자동으로 필요한 시나리오들에 대해 검증을 수행할 수 있으며, 시뮬레이션 등 긴 시간이 걸리는 검증 방법을 최소한으로 사용할 수 있다는 이점을 얻을 수 있다.

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Design and Performance Analysis of Non-coherent Code Tracking Loops for HSDPA MODEM (HSDPA 모뎀용 동기추적회로의 설계 및 성능분석)

  • Yang, Yeon-Sil;Park, Hyung-Rae
    • Journal of Advanced Navigation Technology
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    • v.7 no.1
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    • pp.6-13
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    • 2003
  • In this paper, a non-coherent code tracking loop is designed for 3GPP HSDPA MODEM and its performance is analyzed in terms of steady-state jitter variance and transient response characteristics. Analytical closed-form formula for steady-state jitter variance is first derived for AWGN environments as a function of pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth. Also obtained is the transient response characteristic of a tracking loop. Finally, the performance of the designed tracking loop is confirmed by computer simulations.

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FPGA Implementation of Frequency Offset Cancel Circuit using CORDIC in OFDM (CORDIC을 이용한 OFDM 시스템의 주파수 옵셋 제거 회로의 FPGA 구현)

  • Byon, Kun-Sik
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.5
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    • pp.906-911
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    • 2008
  • This paper designed Simulik Model to cancel the carrier frequency offset in OFDM using CORDIC Algorithm and evaluated its performance. And Simulink Model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model is error free by CORDIC when offset frequency is lower than $10^5MHz$. Also, we verified the performance through Hardware Co-simulation with Xilinx Spartan3 xc3s1000 fg676-4 Target Device, and timing analysis and resource estimation.

FPGA Implementation of BCH Encoder to change code rate (부호율 변경이 가능한 BCH Ecoder의 FPGA구현)

  • Jegal, Dong;Byon, Kun-sik
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.05a
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    • pp.485-488
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    • 2009
  • The class of BCH codes is a large class of error correction codes. HDL implementation of BCH code generator to change code rate. and used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of BCH code generator.

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Analysis of Visual Attention of Students with Developmental Disabilities in Virtual Reality Based Training Contents (가상현실기반 훈련 콘텐츠에서 발달장애인의 시각적 주의집중도 분석)

  • Jo, Junghee
    • Journal of Korea Multimedia Society
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    • v.24 no.2
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    • pp.328-335
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    • 2021
  • In the era of 'Untact', virtual reality-based job training platforms are actively being used as part of non-face-to-face education for students with developmental disabilities. Because the people with developmental disabilities may lack sufficient cognitive abilities, it is difficult to conduct untact training seamlessly without the help of a third party. Therefore, it is necessary for training programs to identify the right timing to provide help so that the training can be continued. This research analyzed the visual attention of students with developmental disabilities in virtual reality-based job training program in order to determine the point of time when an intervention is required by the trainee. Results showed that students who completed the mission tended to have intense visual attention on a small number of objects for a certain period of time; the visual attention of the students who failed tended to shift erratically among multiple objects.

Analysis of Propane and Butane Combustion in a Spark-Ignition Engine under Different Compression Ratio (스파크점화 엔진에서 압축비에 따른 프로판과 부탄의 연소 분석)

  • Hyunwook, Park;Junsun, Lee;Seungmook, Oh;Changup, Kim;Yonggyu, Lee;Kernyong, Kang
    • Journal of ILASS-Korea
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    • v.27 no.4
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    • pp.203-210
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    • 2022
  • Combustion and performance of a spark-ignition engine fueled with propane and butane were analyzed under different compression ratio. The electricity efficiencies of propane and butane increased with increasing the electricity production. The heat release rates of propane and butane were similar at a compression ratio of 9:1 because both fuels had similar optimal ignition timings without knocking combustion. Therefore, the difference in electricity efficiencies of engine generators was insignificant. However, at a higher compression ratio of 11:1, the butane engine generator had a lower electricity efficiency than the propane engine generator because its ignition timing retarded to suppress the knocking combustion.

Analysis for forging of trochoidal gears (트로코이드 기어의 단조 해석)

  • Cho, Hae Yong;Min, Gyu Sik;Choi, Jongung
    • Journal of the Korean Society for Precision Engineering
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    • v.13 no.9
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    • pp.77-83
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    • 1996
  • This paper describes forging of trochoidal gears, which are being widely used in timing belt pulley, pump pulley etc., as a series of development of the simulator for non-axisymmetric elements. Kinematically admissible velocity fields for forging of trochoidal gear were proposed and the loads were calculated by numerical method. When the simulation was carried out, half pith of gear was divided into 6 deformation regions which have different velicity fields by assumptions and boundary conditions. The neutral surface was introduced into forging of trochoidal gears with flat punch and, for each step, it is assumed as a circle with its radius r$_{n}$. The experimental set-up was installed in 200 ton hydraulic press for forging. The billets, of A1 2218 aluminum alloy, were slightly phosphate-coated. It was shown that thd theoretical solutions, as upper bound, are useful to predict the forging load for forging of trochoidal gears, because thdt give estimates that are substantially higher than experimental loads.s.

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Software Implementation of Interrupt Profiler on a Servo-Motor Controller for Timing Analysis (서보 전동기 제어용 임베디드 시스템의 타이밍 분석을 위한 인터럽트 측정 소프트웨어의 구현)

  • Kim, Hee-Jin;Park, Sang-Soo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2011.04a
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    • pp.81-84
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    • 2011
  • 서보 전동기는 탑재된 소프트웨어의 명령에 따라 제어되는 전동기로 다양한 임베디드 응용 분야에서 사용되고 있다. 여러 분야에서 사용되고 있는 만큼 각 응용 분야마다 시간, 부하에 따라 서보 전동기에 요구되는 응답성은 다양하다. 응답성에 민감한 서보 전동기의 소프트웨어를 효율적으로 구현하기 위해서는 다양한 요구사항에 대한 분석이 필수적이다. 본 논문에서는 시간 응답성이 요구되는 서보 전동기의 실제 임베디드 시스템을 위한 인터럽트 측정 소프트웨어를 구현하고, 이에 대한 결과를 제시한다.