• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2621-2624
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• 2003

In this paper, we designed 12Bit DAC(Digital to Analog Converter) that applied to multiple-valued logic system to Binary system. The proposed D/A Converter structure consists of the Binary to Quaternary Converter(BQC) and Quaternary to Analog Converter(QAC). The BQC converts the two input binary signals to the one Digit Quaternary output signal. The QAC converts the Quaternary input signal to the Analog output signal. The proposed DAC structure can implement voltage mode DAC that high resolution low power consumption with reduced chip area. And also, it has advantage of the easy expansion of resolution and fast settling time.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.181-182
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• 2008

In this paper, an cost-effective system architecture is proposed to implement digital predistortion scheme for linearizing the PA amplifing TDD wideband signal. To make digital predistorted signal for compensating nonlinearity of PA, a dedicated ADC and a frequency-down converter are necessary. Proposed scheme is based on the TDD feature that the RF receiver frontend is idle state during the downlink signal processing time and utilize them to make the digital predistorted signal for PA.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.6
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• pp.756-761
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• 2013

This paper propose the new demodulation method that can detect resolver signal's peak at the time of position estimation when the position information is required during current controller period. The proposed method is performed in a synchronous demodulation way with exciting signal and also cover a capability which can compensate the lag element of exciting signal caused by the resolver's inductive component and filter circuit. This paper carried out the experiment to investigate the validity and performance of the suggested method by using the test board made up of DSP and demodulation circuit. The test results show that the proposed method is theoretically clear and work completely as expected from making sure of sampling resolver signal's peak at the time of position estimation. In addition, Software position tracking algorithm is executed with the demodulated signals generated by the suggested method and an exact position can be estimated.

• ETRI Journal
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• v.46 no.2
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• pp.238-249
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• 2024

Equivalent-time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down-conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in-phase/quadrature gain imbalance instead of requiring a high-speed analog-to-digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent-time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent-time sampling using DDC.

• The Journal of the Acoustical Society of Korea
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• v.6 no.3
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• pp.52-59
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• 1987

In this paper, we present a method of realizing an infinite impulse response (IIR) digital filter (DF)using linear delta modulation (LDM) as a simple analog/digital (A/D) converter. This method makes the realization of IIR digital filters much simpler than that of conventional ones because it does not require hardware multipliers and a pulse code modulation (PCM) A/D converter. Compared to the finite impulse respponse (FIR) LDMDF of Lee and Un [1] , this IIR LDMDF requires significantly less computation time.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2411-2413
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• 1998

In this paper, using tile concept of block digital filtering, and the design procedure of time-interleaved oversampling converter are presented. it is shown that arbitrary sigma-delta A/D converter can be converted into corresponding time-interleaved structure. The TIM structure of this paper is designed by the bilinear transform. To verify the simulation results, a second-order TIM structure A/D converter has been implemented and the design process as well as experimented results are presented.

• Journal of the Korea Convergence Society
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• v.7 no.1
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• pp.9-15
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• 2016

In this paper, we describe the design of a high speed data acquisition system(DAS) with STM32 processor based on Cortex-M4. The system is used for the sensor devices to collect raw data on production lines at factory and send them to the servo computer in real time. The system is designed for multi functions with universal asynchronous receiver and transmitter(UART), analog to digital converter(ADC), digital to analog converter(DAC), and general purpose input output(GPIO). those are well tested for various data acquisition and high speed motor control in real time.

• International Journal of Control, Automation, and Systems
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• v.6 no.5
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• pp.670-676
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• 2008

While the matrix converter has many advantages that include bi-directional power flow, a size reduction, a long lifetime, and sinusoidal input currents, it is vulnerable to the input voltage disturbances, because it directly exchanges the input voltage to the output voltage. So, in this paper, a critical evaluation of the effect of various abnormal voltage conditions like unbalanced power supply, balanced non-sinusoidal power supply, input voltage sags and short time blackout of power supply on matrix converter fed induction motor drives is presented. The operation under various abnormal conditions has been analyzed. For this, a 230V, 250VA three phase to three phase matrix converter (MC) fed induction motor drive prototype is implemented using DSP based controller and tests have been carried out to evaluate and improve the stability of system under typical abnormal conditions. Digital storage oscilloscope & power quality analyzer are used for experimental observations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.187-191
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• 2007

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.691-698
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• 2008

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.