• The Transactions of the Korean Institute of Power Electronics
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• v.28 no.1
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• pp.48-58
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• 2023

This paper presents the digital control techniques of a bidirectional CRM(critical-conduction mode) buck(boost) converter, a dead-time design method that optimizes ZVS(zero-voltage switching) and valley-switching operation, and a switching-frequency limitation that ensures stable converter operation. To verify the feasibility of the design, a Si-MOSFET-based bidirectional CRM buck(boost) converter is built with 260-430 V input, 160-240 V output, and 1.0 kW rated capacity. The bidirectional CRM converter achieves an efficiency of up to 99.6% at buck mode and 98.7% at boost mode under rated load conditions.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.346-351
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• 1998

In design of a digital current controller for a 3-phase (3 ) voltage-source (VS) PWM converter, its conventional model, i.e., stationary or synchronous reference frame model, is used in obtaining its discretized version. It introduces, however, inherent errors since the following practical problems are not taken into consideration: the characteristics of the space vector-based pulse-width modulation (SVPWM) and the time delays in the process of sampling and computation. In this paper, the new hybrid reference frame model of the 3 VS PWM converter is proposed considering these problems. In addition, the direct digital current controller based on this model is designed without any prediction or extrapolation algorithm to compensate the time delay. So the control algorithm is made very simple. It represents no steady-state error in input current control and has the optimized transient responses. The validity of the proposed algorithm is proved by the computer simulation and experimental results.

• Journal of Power Electronics
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• v.10 no.5
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• pp.518-527
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• 2010

This paper presents a new technique for directly designing a linear digital controller for a single-phase pulse width modulation (PWM) converter systems, based on closed-loop identification. The design procedure consists of three steps. First, obtain a digital current controller for the inner loop system by using the error space approach, so that the power factor of the supply is close to one. The outer loop is composed of a voltage controller, a current control loop including a current controller, a PWM converter, and a capacitor. Then, all the components, except the voltage controller, are identified by a discrete-time equivalent linear model, using the closed-loop output error (CLOE) method. Based on this equivalent model, a proper digital voltage controller is then directly designed. It is shown through PSim simulations and experimental results that the proposed method is useful for the practical design of PWM converter controllers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• Journal of Electrical Engineering and Technology
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• v.6 no.3
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• pp.375-383
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• 2011

This paper describes a real-time hardware simulator for a grid-tied Permanent Magnet Synchronous Generator (PMSG) wind power system, which consists of an anemometer, a data logger, a motor-generator set with vector drive, and a back-to-back power converter with a digital signal processor (DSP) controller. The anemometer measures real wind speed, and the data is sent to the data logger to calculate the turbine torque. The calculated torque is sent to the vector drive for the induction motor after it is scaled down to the rated simulator power. The motor generates the mechanical power for the PMSG, and the generated electrical power is connected to the grid through a back-to-back converter. The generator-side converter in a back-to-back converter operates in current control mode to track the maximum power point at the given wind speed. The grid-side converter operates to control the direct current link voltage and to correct the power factor. The developed simulator can be used to analyze various mechanical and electrical characteristics of a grid-tied PMSG wind power system. It can also be utilized to educate students or engineers on the operation of grid-tied PMSG wind power system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1619-1626
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• 2021

Unlike traditional delta-sigma analog-to-digital converters, incremental analog-to-digital converters enable 1:1 mapping of input and output through a reset operation, which can be used very easily for multiplexing. Incremental analog-to-digital converters also allow for simpler digital filter designs compared to traditional delta-sigma converters. Therefore, starting with analysis in the time domain of the delayed integrator and non-delayed integrator, which are the basic blocks of analog-to-digital converter design, the design equations of a second-order input feed-forward, extended counting, 2+1 MASH (Multi-stAge-noise-SHaping), 2+2 MASH incremental analog-to-digital converter are derived in this paper. This allows not only prediction of the performance of the incremental analog-to-digital converter before design, but also the design of a digital filter suitable for each analog-to-digital converter. In addition, extended counting and MASH design techniques were proposed to improve the accuracy of analog-to-digital converters.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.135-137
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• 2007

A phase shifted full-bridge PWM converter (PSFBC) has been used as the most popular topology for many applications. But, for the reasons of the cost and performance, the control circuits for the PSFBC have generally been implemented using analog circuits. The studies on the digital control of the PSFBC were recently presented. However, they considered only the digital implementation of the analog controller. This paper presents the modeling and design of the digital controller for the PSFBC in the discrete time domain. The discretized PSFBC model is first derived considering the sampling effect. Based on this model, the digital controller is directly designed in discrete time domain. The simulation and experimental results are provided to verify the proposed modeling and controller design.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.520-521
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• 2017

The converted error is occurred by the time difference between the time interval signal and the clock in a Time-to-Digital Converter of counter-type. If the clock period is $T_{CLOCK}$ the converted error is a maximum $T_{CLOCK}$ by the time difference between the start signal and the clock. And the converted error is a maximum $-T_{CLOCK}$ by the time difference between the stop signal and the clock. However, when the clock is synchronized with the start signal and the colck is generated during the time interval signal the range of converted digital error is from 0 to $(1/2)T_{CLOCK}$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.88-90
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• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.