• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.189-197
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• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• Journal of Power Electronics
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• v.11 no.4
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• pp.471-478
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• 2011

This paper addresses the establishment of a kVA-range plug-in hybrid electrical vehicle (PHEV) integration test platform and associated issues. Advancements in battery and power electronic technology, hybrid vehicles are becoming increasingly dependent on the electrical energy provided by the batteries. Minimal or no support by the internal combustion engine may result in the vehicle being occasionally unable to recharge the batteries during highly dynamic driving that occurs in urban areas. The inability to sustain its own energy source creates a situation where the vehicle must connect to the electrical grid in order to recharge its batteries. The effects of a large penetration of electric vehicles connected into the grid are still relatively unknown. This paper presents a novel methodology that will be utilized to study the effects of PHEV charging at the sub-transmission level. The proposed test platform utilizes the power hardware-in-the-loop (PHIL) concept in conjunction with high-fidelity PHEV energy system simulation models. The battery, in particular, is simulated utilizing a real-time digital simulator ($RTDS^{TM}$) which generates appropriate control commands to a power electronics-based voltage amplifier that interfaces via a LC-LC-type filter to a power grid. In addition, the PHEV impact is evaluated via another power electronic converter controlled through $dSPACE^{TM}$, a rapid control systems prototyping software.

• Journal of the Korean Society for Nondestructive Testing
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• v.9 no.1
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• pp.30-38
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• 1989

Since the nuclear power plants in Korea have been operated in 1979, the nondestructive testing (NDT) of pressure vessels and/or piping welds plays an important role for maintaining the safety and integrity of the plants. Ultrasonic method is superior to the other NDT method in the viewpoint of the detectability of small flaw and accuracy to determine the locations, sizes, orientations, and shapes. As the service time of the nuclear power plants is increased, the radiation level from the components is getting higher. In order to get more quantitative and reliable results and secure the inspector from the exposure to high radiation level, automation of the ultrasonic equipments has been one of the important research and development(R & D) subject. In this research, it was attempted to visualize the shape of flaws presented inside the specimen using a Modified C-Scan technique. In order to develope Modified C-Scan technique, an automatic ultrasonic scanner and a module to control the scanner were designed and fabricated. IBM-PC/XT was interfaced to the module to control the scanner. Analog signals from the SONIC MARK II were digitized by Analog-Digital Converter(ADC 0800) for Modified C-Scan display. A computer program has been developed and has capability of automatic data acquisition and processing from the digital data, which consist of maximum amplitudes in each gate range and locations. The data from Modified C-Scan results was compared with shape from artificial defects using the developed system. Focal length of focused transducer was measured. The automatic ultrasonic equipment developed through this study is essential for more accurate, reliable, and repeatable ultrasonic experiments. If the scanner are modified to meet to appropriate purposes, it can be applied to automation of ultrasonic examination of nuclear power plants and helpful to the research on ultrasonic characterization of the materials.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.697-701
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• 1996

King Sejong's Striking water-clock which brought in use on the first of July in 1434 was mainly composed of timekeeping and time announcing parts signalling twelve double-hours, and five night-watches and night-watch-divisions automatically by means of ball-operating jackworks. The clock was arranged with dual timekeeping system, the one for a full day(twelve double-hours) and the other for five night-watches achieving twelve double-hours and one-hundred interval horary systems. The vessels were arrayed in inflow-type water-clock, a large reservoir on the highest story, a constant-level tank for supplying water to the measuring vessel evenly in the middle, and the lowest tank to receive water from the above constant-level tank. An indicator-rod on the float was raised upwards depending on the water-level increase to show timing scales and also to release small bronze balls from the ball-rack mechanisms implanted on the measuring vessel to signal timing intervals.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.75-81
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• 2021

This study analyzes the resonance characteristics caused by the mutual interference between LCL filters and the grid impedance under the parallel operation of the grid-connected inverter using the LCL filter. These characteristics are verified through simulation and experiment. Two inverters are used to connect to the grid in parallel, and the system parameters, including the LCL filter, are set to the same conditions. In the case of inverters running in parallel at the point of common coupling, the presence of grid impedance causes mutual interference between the LCL filters of each inverter, and the deviation of the filter resonance frequency is analyzed to understand the parallel inverter. The correlation between the number of devices and the size of grid impedance is simulated by PSIM and verified by MATLAB. By connecting the real-time digital simulator Typhoon HILS to the DSP 28377 control board, the mutual interference characteristics are tested under the condition of two inverters running in parallel. The experimental and analysis results are the same, indicating the validity of the analysis.

• Journal of Sensor Science and Technology
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• v.13 no.5
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• pp.383-391
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• 2004

In this study, we implemented the pulse transit time (PTT) system to examine usefulness of the monitoring method of distensibility and elasticity using photoplethysmography sensor in vivo. PTT is defined as the time interval between the peak of QRS complex in ECG signal and the maximum slope point of photoplethysmography. these two signals were converted to digital data by means of AID converter, then PTT was evaluated by heartbeat using PC. Results of analysis were displayed as a graph using spline interpolation method. The variance of PTT was measured repetitiously to verify efficiency of PTT system in resting state and hyperemic state. Repeated measurement of PTT was not same value but showed that coefficients of correlation were related with each other as 0.8302 (P<0.01) in resting state. And also repeated measurement of PTT showed significant correlation as 0.868 (P<0.01) in the hyperemic state. These result showed that PTT is reflect on transient pressure variance in the artery and is very useful method for the evaluation of prognosis of the hypertension and arteriosclerosis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Journal of Power Electronics
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• v.10 no.4
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• pp.342-350
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• 2010

Randomizing the switching frequency (RSF) to reduce the electromagnetic interference (EMI) of switching power converters is a well-known technique that has been previously discussed. The randomized pulse position (RPP) technique, in which the switching frequency is kept fixed while the pulse position (the delay from the starting of the switching cycle to the turn-on instant within the cycle) is randomized, has been previously addressed in the literature for the same purpose. This paper presents a double-hybrid technique (DHB) for EMI reduction in dc-dc switching regulators. The proposed technique employed both the RSF and the RPP techniques. To effectively spread the conducted-noise frequency spectrum and at the same time attain a satisfactory output voltage quality, two parameters (switching frequency and pulse position) were randomized, and a third parameter (the duty ratio) was controlled by a digital compensator. Implementation was achieved using field programmable gate array (FPGA) technology, which is increasingly being adopted in industrial electronic applications. To evaluate the contribution of the proposed DHB technique, investigations were carried out for each basic PWM, RPP, RSF, and DHB technique. Then a comparison was made of the performances achieved. The experimentally investigated features include the effect of each technique on the common-mode, differential-mode, and total conducted-noise characteristics, and their influence on the converter’s output ripple voltage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.1
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• pp.90-97
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• 2001

A high frequency resonant inverter consisting of iliree unit Half-Bridge serial resommt inverter used as power source of induction heatmg at high frequency is presented in this paper. As a output [Dwer control strategy, sequencial time-sharing gate contml methcd is applied. This methcd is TDM(Time Division Multiplexing), which is broadly used with digital and analog signals transmission in communication system 1be analysis of the proposed circuit is generally described by using the normalized pararmenters. Also, the principle of basic operating and the its characteristics are estimated by the parameters such as switching frequency, load resistance. Also, according to the calculated characteristics value, a method of the circuit design and operating characteristics of the inverter is proposed. This paper proves the validity of theoretical analysis through the Pspice. This proposed inverter show that it can be practically used in future as power source system for induction heating application, DC-DC converter etc. r etc.