• Journal of Power Electronics
• /
• 제16권3호
• /
• pp.823-831
• /
• 2016

A high-efficiency method is proposed to suppress magnetic core imbalance in phase-shifted full-bridge (PSFB) converters. Compared with conventional solutions, such as controlling peak current mode (PCM) or adding DC blocking capacitance, the proposed method has several advantages, such as lower power loss and smaller size, because the additional current sensor or blocking capacitor is removed. A time domain model of the secondary side is built to analyze the relationship between transformer core imbalance and cathode voltage of secondary side rectifiers. An approximate control algorithm is designed to achieve asymmetric phase control, which reduces the effects of imbalance. A 60 V/15 A prototype is built to verify the proposed method. Experimental results show that the numerical difference of primary side peak currents between two adjacent cycles is suppressed from 2 A to approximately 0 A. Meanwhile, compared with the PCM solution, the efficiency of the PSFB converter is slightly improved from 93% to 93.2%.

• Journal of Power Electronics
• /
• 제14권3호
• /
• pp.444-457
• /
• 2014

This paper presents the design and realization of a digital PV simulator with a Push-Pull Forward (PPF) circuit based on the principle of modular hardware and configurable software. A PPF circuit is chosen as the main circuit to restrain the magnetic biasing of the core for a DC-DC converter and to reduce the spike of the turn-off voltage across every switch. Control and I/O interface based on a personal computer (PC) and multifunction data acquisition card, can conveniently achieve the data acquisition and configuration of the control algorithm and interface due to the abundant software resources of computers. In addition, the control program developed in Matlab/Simulink can conveniently construct and adjust both the models and parameters. It can also run in real-time under the external mode of Simulink by loading the modules of the Real-Time Windows Target. The mathematic models of the Push-Pull Forward circuit and the digital PV simulator are established in this paper by the state-space averaging method. The pole-zero cancellation technique is employed and then its controller parameters are systematically designed based on the performance analysis of the root loci of the closed current loop with $k_i$ and $R_L$ as variables. A fuzzy PI controller based on the Takagi-Sugeno fuzzy model is applied to regulate the controller parameters self-adaptively according to the change of $R_L$ and the operating point of the PV simulator to match the controller parameters with $R_L$. The stationary and dynamic performances of the PV simulator are tested by experiments, and the experimental results show that the PV simulator has the merits of a wide effective working range, high steady-state accuracy and good dynamic performances.

• 융합신호처리학회논문지
• /
• 제12권2호
• /
• pp.139-144
• /
• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Journal of Power Electronics
• /
• 제19권1호
• /
• pp.119-133
• /
• 2019

Although the dual modulation wave method can solve the low-frequency neutral point potential (NPP) fluctuation problem for three-level neutral point clamped converters, it also increases the switching frequency and limits the zero-sequence voltage. That makes it harmful when dealing with the NPP drift problem if the converter suffers from a long dead time or asymmetric loads. By introducing two degrees of freedom (2-DOF), an NPP control based on a search optimization method can demonstrate its ability to cope with the above mentioned two types of NPP problems. However, the amount of calculations for obtaining an optimal 2-DOF is so large that the method cannot be applied to certain industrial applications with an inexpensive digital signal processor. In this paper, a novel optimal 2-DOF-based NPP control is proposed. The relationships between the NPP and the 2-DOF are analyzed and a method for directly determining the optimal 2-DOF is also discussed. Using a direct calculation method, the amount of calculations is significantly reduced. In addition, the proposed method is able to maintain the strongest control ability for the two types of NPP problems. Finally, some experimental results are given to confirm the validity and feasibility of the proposed method.

• 전자공학회논문지
• /
• 제54권2호
• /
• pp.47-52
• /
• 2017

본 논문에서는 생체 신호 처리를 위한 중간 속도를 갖는 A/D 변환기 설계를 위하여 1.8V 전원의 CMOS SAR(Successive Approximation Register) A/D 변환기를 설계하였다. 본 논문에서 C-DAC Array의 MSB단을 4분할하여 선형성을 향상시킨 10비트 SAR A/D 변환기 설계를 제안한다. 아날로그 입력이 인가되는 MSB 단의 전하가 충전되는 시간을 확보하여 선형성을 높였다. MSB단이 아날로그 입력을 샘플링하는 블록이기 때문에 초기 값을 보다 정교하게 받아들이는 원리를 통해 선형성을 확보하였다. C-DAC에서 Split 커패시터를 사용하여 면적을 최소화하고, 전력을 감소시켰다. 제안된 SAR A/D 변환기는 0.18um CMOS 공정을 이용하여 설계하였고, 공급 전압 1.8V에서 4MS/s의 변환속도를 가지며, 7.5비트의 ENOB(Effective Number of Bit)이 측정되었다. $850{\times}650um^2$의 면적, 총 전력소모는 123.105uW이고, 170.016fJ/step의 FOM(Figure of Merit)을 확인할 수 있다.

• 한국항행학회논문지
• /
• 제16권5호
• /
• pp.839-845
• /
• 2012

본 논문에서는 임베디드 웹 서버(Embedded Web Server)를 이용하여 원격에서 다양한 입출력 장치들의 상태를 계측하거나 이들을 제어하는 시스템을 설계하고 개발한다. 설계된 원격 제어 및 계측시스템은 Cortex-M3 ARM 마이크로컨트롤러를 사용하여 구현되었으며, 제어 및 계측 시스템 사용자를 위한 사용자 응용 프로그램, 그리고 디지틀 입출력 장치, AD/DAC, LCD 및 온습도 센서 등의 구동장치 프로그램 및 이벤트 처리를 위한 웹서버 프로그램을 구현하였다. 각각의 프로그램은 Eclipse 개발환경을 구축하여 Codesourcery C 언어, Java script, 그리고 HTML 언어를 사용하여 작성되었다. 본 논문에서 구현된 제어 및 계측 시스템의 실험결과는 실제로 실시간 실험을 통해, 설계된 바와 같이 사용자가 원하는 동작을 정확하게 수행하는 것을 확인하였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
• /
• pp.77-81
• /
• 2004

In this paper, we propose a analog front-end (AFE) for noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection. The proposed AFE are designed using 0.18 micron CMOS technology and verified by simulation using SPICE. The proposed AFE consist of Sample-and-Hold block, Analog-to-Digital converter, synchronizer, delayed clock generator and impulse generator. The time resolution of 1ns is obtained with 100MHz system clocks and the synchronized 10-bit digital outputs are delivered to the baseband. The impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results show the feasibility of the proposed UWB AFE systems.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권3호
• /
• pp.352-358
• /
• 2016

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.

• 대한전자공학회논문지SP
• /
• 제46권5호
• /
• pp.32-39
• /
• 2009

Compressed Sensing (이하 압축 감지 기술)은 Nyquist 률 이하로 아날로그 신호를 샘플 할 수 있는 기법이다. 이 기법으로 신호는 기존의 신호 샘플 방법보다 적은 수의 측정값으로 표현이 가능하며 또한 선형 프로그래밍을 이용하여 측정값으로부터 본래 신호를 높은 확률로 복원할 수 있다. 이를 통해 압축 감지 기술은 같은 신호를 획득하는데 소모되는 측정 시간 및 ADC (analog-to-digital converter) 자원의 양을 크게 감소시키는 장점을 갖는다. 본 논문에서는 압축 감지 기술에 대한 기본적인 개념과 임의 기저를 이용하여 아날로그 신호로부터 측정값을 획득하는 방법과 본래 신호를 복원하는 방법에 대해 설명하고 무선통신 분야에서의 압축 감지 기술 응용 예시를 소개한다.

• Journal of Power Electronics
• /
• 제18권2호
• /
• pp.558-572
• /
• 2018

In addition to its modular nature, a Hybrid Modular Multilevel Converter (HMMC) assembled from half-bridge and full-bridge sub-modules, is able to block DC faults with a minimum number of switching devices, which makes it attractive for high power applications. This paper introduces a control strategy based on the Root-Least Square (RLS) algorithm to estimate the capacitor voltages instead of using direct measurements. This action eliminates the need for voltage transducers in the HMMC sub-modules and the associated communication link with the central controller. In addition to capacitor voltage balancing and suppression of circulating currents, a fault tolerant control unit (FTCU) is integrated into the proposed strategy to modify the parameters of the HMMC controller. On advantage of the proposed FTCU is that it does not need extra components. Furthermore, a fault detection unit is adapted by utilizing a hybrid estimation scheme to detect sub-module faults. The behavior of the suggested technique is assessed using PSCAD offline simulations. In addition, it is validated using a real-time digital simulator connected to a real time controller under various normal and fault conditions. The proposed strategy shows robust performance in terms of accuracy and time response since it succeeds in stabilizing the HMMC under faults.